公开(公告)号：US07782107B2

公开(公告)日：2010-08-24

申请号：US12165578

申请日：2008-06-30

申请人： Anand Dixit

发明人： Anand Dixit

IPC分类号： H03K3/356

CPC分类号： H03K19/00338 ,  H03K3/0375 ,  H03K3/356173

摘要： An apparatus for an event tolerant circuit including a latch. The event tolerant circuit may maintain correct data values even after the occurrence of an event such as a soft error. The event tolerant circuit may introduce a delay in a feedback loop, thereby passing the glitch value to an element in the feedback loop at different times, thus preventing the propagation of the glitch through the event tolerant circuit.

摘要翻译： 一种用于包括闩锁的容错电路的装置。 事件容忍电路即使在诸如软错误的事件发生之后也可以保持正确的数据值。 事件容忍电路可能在反馈回路中引入延迟，从而在不同时间将毛刺值传递给反馈回路中的元件，从而防止毛刺通过事件容限电路的传播。

公开(公告)号：US20090322401A1

公开(公告)日：2009-12-31

申请号：US12165578

申请日：2008-06-30

申请人： Anand Dixit

发明人： Anand Dixit

IPC分类号： H03L5/00

CPC分类号： H03K19/00338 ,  H03K3/0375 ,  H03K3/356173

摘要： An apparatus for an event tolerant circuit including a latch. The event tolerant circuit may maintain correct data values even after the occurrence of an event such as a soft error. The event tolerant circuit may introduce a delay in a feedback loop, thereby passing the glitch value to an element in the feedback loop at different times, thus preventing the propagation of the glitch through the event tolerant circuit.

摘要翻译： 一种用于包括闩锁的容错电路的装置。 事件容忍电路即使在诸如软错误的事件发生之后也可以保持正确的数据值。 事件容忍电路可能在反馈回路中引入延迟，从而在不同时间将毛刺值传递给反馈回路中的元件，从而防止毛刺通过事件容限电路的传播。

公开(公告)号：US06744838B1

公开(公告)日：2004-06-01

申请号：US09645869

申请日：2000-08-24

申请人： Anand Dixit

发明人： Anand Dixit

IPC分类号： H03D324

CPC分类号： H03D13/003 ,  H03L7/089 ,  H03L7/095

摘要： A detector digitally monitors and detects when an oscillating signal output by a phase-locked-loop (PLL) is locked to a reference signal input to the PLL. The PLL includes a phase frequency detector that outputs an up signal and a down signal that each has a pulse width. When the oscillating signal is locked to the reference signal, the pulse widths of the up and down signals are equal. The detector detects when the pulse widths are unequal, and outputs a lock status signal that indicates this condition.

摘要翻译： 检测器数字监控和检测何时由锁相环（PLL）输出的振荡信号锁定到输入到PLL的参考信号。 PLL包括相位频率检测器，其输出各自具有脉冲宽度的上升信号和下降信号。 当振荡信号被锁定到参考信号时，上下信号的脉冲宽度相等。 检测器检测脉冲宽度不等时，并输出指示此条件的锁定状态信号。

公开(公告)号：US08525566B2

公开(公告)日：2013-09-03

申请号：US13210587

申请日：2011-08-16

申请人： Anand Dixit ,  Robert P. Masleid

发明人： Anand Dixit ,  Robert P. Masleid

IPC分类号： H03K3/00

CPC分类号： H03K3/0375 ,  H03K3/356156

摘要： A repeater circuit is disclosed. The circuit includes an input stage configured to receive an input signal and a clock signal. An output stage is configured to drive an output signal on an output node to a first state responsive to a first transition of the input signal on the input node concurrent with a first phase of the clock signal. The input stage is configured to activate a first driver circuit of the output stage responsive to a first transition of the input signal. A reverse stage is configured to assert a first inhibit signal at a delay time subsequent to activation of the first driver circuit, which is configured to be deactivated responsive to assertion of the first inhibit signal. Assertion of the first inhibit signal is prevented responsive to a second transition of the input data signal occurring before the delay time has elapsed.

摘要翻译： 公开了一种中继器电路。 电路包括被配置为接收输入信号和时钟信号的输入级。 输出级被配置为响应于输入节点上的输入信号的第一次转换与时钟信号的第一相位并行地将输出节点上的输出信号驱动到第一状态。 输入级被配置为响应于输入信号的第一转换而激活输出级的第一驱动器电路。 反向级被配置为在激活第一驱动器电路之后的延迟时间断言第一禁止信号，其被配置为响应于断言第一禁止信号而被去激活。 响应于在延迟时间过去之前发生的输入数据信号的第二转变来阻止第一禁止信号的断言。

公开(公告)号：US08525550B2

公开(公告)日：2013-09-03

申请号：US12908167

申请日：2010-10-20

申请人： Robert P. Masleid ,  Anand Dixit

发明人： Robert P. Masleid ,  Anand Dixit

IPC分类号： H03K19/096 ,  H04B3/36

CPC分类号： H04B3/36 ,  H03K3/356008 ,  H03K17/693

摘要： A circuit implementing multiplexer, storage, and repeater functions is disclosed. The circuit includes first and second input stages having first and second data inputs, respectively. An output stage is configured to drive an output signal. The first input stage is configured to activate the output stage responsive to a first condition, while the second input stage is configured to activate the output stage responsive to a second condition. An intermediate stage is configured to deactivate the output stage at a first delay time subsequent to one of the first or second input stages activating the output stage. The repeater circuit also includes a storage element configured to store a state of the output signal, and further configured to cause the output node to be held at the state of the output signal subsequent to deactivation of the output stage.

摘要翻译： 公开了实现多路复用器，存储和转发器功能的电路。 电路包括分别具有第一和第二数据输入的第一和第二输入级。 输出级被配置为驱动输出信号。 第一输入级被配置为响应于第一状态激活输出级，而第二输入级被配置为响应于第二状态激活输出级。 中间级被配置为在第一或第二输入级中的一个激活输出级之后的第一延迟时间停用输出级。 中继器电路还包括存储元件，其被配置为存储输出信号的状态，并且还被配置为使输出节点在输出级的去激活之后保持在输出信号的状态。

公开(公告)号：US20110254669A1

公开(公告)日：2011-10-20

申请号：US12759833

申请日：2010-04-14

申请人： Anand Dixit ,  Robert P. Masleid

发明人： Anand Dixit ,  Robert P. Masleid

IPC分类号： G08B1/00

CPC分类号： G01R31/318541

摘要： A repeater circuit is disclosed. The repeater circuit includes an input circuit coupled to receive a data input signal and a clock signal, and an output circuit configured to, when activated, drive an output signal on an output node. The input circuit is further configured to activate the output circuit in order to initiate a logical transition of the data output signal. A deactivation circuit is configured to deactivate the output circuit at a delay subsequent to activation. A latch is coupled the output circuit and it is configured to change a latch output state responsive to activation of the output circuit. The latch is configured to hold a state the output node subsequent to deactivation of the output circuit. The input circuit is configured to activate the output circuit dependent on the clock signal. The deactivation circuit is configured to deactivate the output circuit independent of the clock signal.

摘要翻译： 公开了一种中继器电路。 中继器电路包括耦合以接收数据输入信号和时钟信号的输入电路，以及被配置为在被激活时驱动输出节点上的输出信号的输出电路。 输入电路还被配置为激活输出电路以便启动数据输出信号的逻辑转换。 禁用电路被配置为在激活之后以延迟来去激活输出电路。 锁存器耦合输出电路，并且其配置成响应于输出电路的激活而改变锁存器输出状态。 锁存器被配置为在输出电路去激活之后保持输出节点的状态。 输入电路被配置为根据时钟信号激活输出电路。 停用电路被配置为独立于时钟信号去激活输出电路。

公开(公告)号：US20100327982A1

公开(公告)日：2010-12-30

申请号：US12495088

申请日：2009-06-30

申请人： Anand Dixit ,  Robert P. Masleid

发明人： Anand Dixit ,  Robert P. Masleid

IPC分类号： G01R23/00 ,  H03K3/03

CPC分类号： H03K3/0315 ,  H03K3/02

摘要： The described embodiments provide a configurable pulse generator circuit. More specifically, the described embodiments include a pulse generator circuit; an inverting difference oscillator (IDO) enabling circuit coupled to the pulse generator circuit; and a disable signal coupled to the IDO enabling circuit. When the disable signal is asserted, the IDO enabling circuit is disabled and the pulse generator circuit is configured as a pulse generator. In contrast, when the disable signal is deasserted, the IDO enabling circuit is enabled and the pulse generator circuit is configured as part of an IDO.

摘要翻译： 所描述的实施例提供可配置的脉冲发生器电路。 更具体地，所描述的实施例包括脉冲发生器电路; 反相差分振荡器（IDO）使能电路耦合到脉冲发生器电路; 以及耦合到IDO使能电路的禁用信号。 当禁用信号被断言时，禁用IDO使能电路，脉冲发生器电路被配置为脉冲发生器。 相反，当禁用信号无效时，启用IDO使能电路，并将脉冲发生器电路配置为IDO的一部分。

公开(公告)号：US07797596B2

公开(公告)日：2010-09-14

申请号：US11861403

申请日：2007-09-26

申请人： Anand Dixit ,  Raymond A. Heald ,  Steven R. Boyle

发明人： Anand Dixit ,  Raymond A. Heald ,  Steven R. Boyle

IPC分类号： G11C29/00

CPC分类号： G01R31/3187

摘要： A method for testing an integrated circuit implemented in an electronic system. The method includes placing an integrated circuit (or portion thereof) that is implemented in an operational system (e.g., in a computer system) in an offline status. An electrical parameter of the integrated system (e.g., a voltage, clock frequency, etc.) is set, and a built-in self-test (BIST) is conducted. Any failures that occur during the BIST are recorded. Testing is then repeated for each of a plurality of predetermined values of the electrical parameter, recording any failures that occur. Once testing is complete a failure rate/range is determined for each of the predetermined values.

摘要翻译： 一种用于测试在电子系统中实现的集成电路的方法。 该方法包括在离线状态下放置在操作系统（例如，计算机系统）中实现的集成电路（或其部分）。 设置集成系统的电参数（例如，电压，时钟频率等），并且进行内置自检（BIST）。 记录在BIST期间发生的任何故障。 然后针对电参数的多个预定值中的每一个重复测试，记录发生的任何故障。 一旦测试完成，则为每个预定值确定故障率/范围。