公开(公告)号：US12003236B2

公开(公告)日：2024-06-04

申请号：US17688482

申请日：2022-03-07

申请人： Kioxia Corporation

发明人： Ryuji Takahashi ,  Kazuya Matsuzawa

IPC分类号： H03K19/003 ,  H03K19/0185

CPC分类号： H03K19/00338 ,  H03K19/018521

摘要： A semiconductor device includes: an electronic circuit to receive a first signal and transmit a second signal; a power supply circuit to supply a power supply voltage to the electronic circuit; and a correction circuit to change a value of the power supply voltage to switch between a normal and a refresh operation mode. The electronic circuit includes: a first Pch transistor in which a potential of a first gate changes according to the first signal, and a potential of one of the first source and drain changes in response to the power supply voltage; and a first Nch transistor in which the second gate is electrically connected to the first gate, a potential of one of the second source and drain is equal to or lower than a ground potential, and another of the second source and drain is electrically connected to another of the first source and drain.

公开(公告)号：US09754681B2

公开(公告)日：2017-09-05

申请号：US15446909

申请日：2017-03-01

申请人： STMicroelectronics S.r.l.

发明人： Ignazio Bruno Mirabella ,  Salvatore Pappalardo ,  Calogero Ribellino ,  Alessandro Nicolosi

IPC分类号： G11C17/18 ,  G11C17/16

CPC分类号： G11C17/18 ,  G11C11/4125 ,  G11C17/16 ,  H03K3/02335 ,  H03K19/00338 ,  H03K19/17764

摘要： A radiation hardened memory cell includes an odd number of storage elements configured to redundantly store an input data logic signal. The storage elements include output lines for outputting respective logic signals having respective logic values. A logic combination network receives the respective logic signals and is configured to generate an output signal having a same logic value as a majority of the logic signals output from the storage elements. An exclusive logic sum circuit receives the respective logic signals output from the storage elements and is configured to produce a refresh of the logic data signal as stored in the storage elements when one of the logic signals output from the storage elements undergoes a logic value transition due to an error event.

公开(公告)号：US20170207784A1

公开(公告)日：2017-07-20

申请号：US15453646

申请日：2017-03-08

申请人： ARM Ltd.

发明人： Shidhartha Das ,  Anand Savanth ,  David Bull

IPC分类号： H03K19/003 ,  H03K19/0175

CPC分类号： H03K19/00323 ,  H03K19/00315 ,  H03K19/00338 ,  H03K19/017581

摘要： According to one embodiment of the present disclosure, a circuit includes a Correlated Electron Switch (CES) element and a programming circuit. The CES element includes a first input. The first input of the CES element is coupled to an input signal to be monitored. The CES element is programmed in a first impedance state. The programming circuit coupled to the CES element is configured to switch the CES element from the first impedance state to a second impedance state in response to a voltage transition on the input signal. The voltage transition indicates a fault event. The output element coupled to the first input of the CES element determines that the transition has occurred responsive to the CES element switching to the second impedance state.

公开(公告)号：US08884643B2

公开(公告)日：2014-11-11

申请号：US13557790

申请日：2012-07-25

申请人： Michael Augustin ,  Michael Goessel ,  Rolf Kraemer

发明人： Michael Augustin ,  Michael Goessel ,  Rolf Kraemer

IPC分类号： H03K19/003 ,  H03K19/23 ,  H03K19/20 ,  H03K19/007

CPC分类号： H03K19/00392 ,  H03K19/00338 ,  H03K19/0075 ,  H03K19/20

摘要： Electronic circuit arrangement for processing binary input values xεX of a word width n (n>1), with a first, second and third combinatory circuit components configured to process the binary input values x to form first, second and third binary output values. The arrangement further includes a majority voter element configured to receive the binary output values and provide a majority signal based on the received binary output values. The second and third combinatory circuit components are designed, as regards faults during processing of the binary input values x in the first combinatory circuit component, to process binary input values of a true non-empty partial quantity X1 of the quantity of binary input values X in a fault-tolerant manner and process binary input values of a further non-empty partial quantity X2 of the quantity of binary input values X different from the true non-empty partial quantity X1 in a fault-intolerant manner.

摘要翻译： 用于处理单词宽度n（n> 1）的二进制输入值x和e的电子电路装置，其中第一组合电路组件被配置为处理二进制输入值x以形成第一，第二和第三二进制输出值 。 该布置还包括被配置为接收二进制输出值并且基于接收到的二进制输出值提供多数信号的多数选民元素。 第二组合电路组件和第三组合电路组件被设计为关于处理第一组合电路组件中的二进制输入值x的故障，以处理二进制输入值X的真实非空部分量X1的二进制输入值 以容错方式处理二进制输入值X的另一非空部分量X2的二进制输入值，该二进制输入值X以不容错误的方式与真实非空部分数量X1不同。

公开(公告)号：US20140015564A1

公开(公告)日：2014-01-16

申请号：US13550462

申请日：2012-07-16

申请人： Ethan Cannon ,  Salim Rabaa ,  Josh Mackler

发明人： Ethan Cannon ,  Salim Rabaa ,  Josh Mackler

IPC分类号： H03K19/003 ,  H01L21/82

CPC分类号： H03K19/20 ,  H03K19/00338

摘要： A circuit and methods for mitigating radiation-induced Single Event Effects (SEE) in Silicon-on-Insulator (SOI) Complementary Metal-Oxide-Semiconductor (CMOS) integrated circuits are presented. A primary logic output is generated from a primary logic gate in response to an input. A redundant logic output is generated from a redundant logic gate that duplicates the primary logic output in response to the input if an SEE is not present. An interleaved C-gate output is generated from an interleaved C-gate that emulates an inverter output when the primary logic output and the redundant logic output match, and does not changes its output when the primary logic output and the redundant logic output do not match during the SEE.

摘要翻译： 介绍了一种用于减轻绝缘体上硅（SOI）互补金属氧化物半导体（CMOS）集成电路中的辐射诱发单事件效应（SEE）的电路和方法。 响应于输入，从主逻辑门产生主逻辑输出。 如果不存在SEE，则从冗余逻辑门产生冗余逻辑输出，该逻辑门复制主逻辑输出以响应输入。 当主逻辑输出和冗余逻辑输出匹配时，交错C门输出从仿真反相器输出的交错C门产生，当主逻辑输出与冗余逻辑输出不匹配时，不会改变其输出 在SEE期间。

公开(公告)号：US08497701B2

公开(公告)日：2013-07-30

申请号：US13300255

申请日：2011-11-18

申请人： Sylvain Clerc ,  Gilles Gasiot ,  Maximilien Glorieux

发明人： Sylvain Clerc ,  Gilles Gasiot ,  Maximilien Glorieux

IPC分类号： H03K17/16 ,  H03K3/037

CPC分类号： H03K19/00338

摘要： The present invention relates to an integrated electronic circuit including elements enabling to implement a logic function and means for attenuating the sensitivity of said elements to external disturbances, said attenuation means being disconnectable during phases of intentional modification of the state of said elements.

摘要翻译： 本发明涉及一种集成电子电路，其包括能够实现逻辑功能的元件和用于衰减所述元件对外部干扰的灵敏度的装置，所述衰减装置在有意修改所述元件的状态的阶段期间可断开。

公开(公告)号：US20130099796A1

公开(公告)日：2013-04-25

申请号：US13279049

申请日：2011-10-21

申请人： Charles Parkhurst ,  Mark Hamlyn

发明人： Charles Parkhurst ,  Mark Hamlyn

IPC分类号： G01R31/00

CPC分类号： G01R19/16571 ,  H03K19/00338

摘要： Systems and methods for radiation-tolerant overcurrent detection are disclosed. In some embodiments, an integrated circuit may include a plurality of overcurrent detectors, each of the plurality of overcurrent detectors configured to detect a candidate overcurrent event. The integrated circuit may also include a voting circuit coupled to the overcurrent detectors, the voting circuit configured to indicate an overcurrent in response to receiving a selected number of candidate overcurrent events from the overcurrent detectors. At least one of the overcurrent detectors may be subject to detecting the candidate overcurrent in error, at least in part, due to exposure to ionizing radiation.

摘要翻译： 公开了辐射耐受过电流检测的系统和方法。 在一些实施例中，集成电路可以包括多个过电流检测器，多个过电流检测器中的每一个配置成检测候选过电流事件。 集成电路还可以包括耦合到过电流检测器的投票电路，投票电路被配置为响应于从过电流检测器接收到选定数量的候选过电流事件而指示过电流。 过电流检测器中的至少一个可能由于暴露于电离辐射而至少部分地错误地检测候选过电流。

公开(公告)号：US20130002288A1

公开(公告)日：2013-01-03

申请号：US13557790

申请日：2012-07-25

申请人： Michael Augustin ,  Michael Goessel ,  Rolf Kraemer

发明人： Michael Augustin ,  Michael Goessel ,  Rolf Kraemer

IPC分类号： H03K19/003

CPC分类号： H03K19/00392 ,  H03K19/00338 ,  H03K19/0075 ,  H03K19/20

摘要： Electronic circuit arrangement for processing binary input values xεX of a word width n (n>1), with a first, second and third combinatory circuit components configured to process the binary input values x to form first, second and third binary output values. The arrangement further includes a majority voter element configured to receive the binary output values and provide a majority signal based on the received binary output values. The second and third combinatory circuit components are designed, as regards faults during processing of the binary input values x in the first combinatory circuit component, to process binary input values of a true non-empty partial quantity X1 of the quantity of binary input values X in a fault-tolerant manner and process binary input values of a further non-empty partial quantity X2 of the quantity of binary input values X different from the true non-empty partial quantity X1 in a fault-intolerant manner.

摘要翻译： 用于处理单词宽度n（n> 1）的二进制输入值x和e的电子电路装置，其中第一组合电路组件被配置为处理二进制输入值x以形成第一，第二和第三二进制输出值 。 该布置还包括被配置为接收二进制输出值并且基于接收到的二进制输出值提供多数信号的多数选民元素。 第二组合电路组件和第三组合电路组件被设计为关于处理第一组合电路组件中的二进制输入值x的故障，以处理二进制输入值X的真实非空部分量X1的二进制输入值 以容错方式处理二进制输入值X的另一非空部分量X2的二进制输入值，该二进制输入值X以不容错误的方式与真实非空部分数量X1不同。

公开(公告)号：US08230279B2

公开(公告)日：2012-07-24

申请号：US12932201

申请日：2011-02-19

申请人： Michael Nicolaidis

发明人： Michael Nicolaidis

IPC分类号： G01R31/3177 ,  G01R31/40

CPC分类号： G06F11/10 ,  H03K19/00338

摘要： The invention concerns a circuit protected against transitory perturbations, comprising a combinatorial logic circuit (10), having at least an output (A); a circuit (20) generating an error control code for said output, and a storage element (24) provided at said output, controlled by the circuit generating a control code to be transparent when the control code is correct, and to maintain its status when the control code is incorrect.

摘要翻译： 本发明涉及一种防止瞬时扰动的电路，包括具有至少一个输出（A）的组合逻辑电路（10）; 产生用于所述输出的错误控制代码的电路（20）和设置在所述输出端的存储元件（24），所述存储元件（24）由所述电路控制，所述电路在所述控制代码正确时产生要透明的控制代码，并且当 控制代码不正确。

公开(公告)号：US20120185816A1

公开(公告)日：2012-07-19

申请号：US13277135

申请日：2011-10-19

申请人： Klas Olof Lilja

发明人： Klas Olof Lilja

IPC分类号： G06F17/50

CPC分类号： G06F17/5022 ,  G06F17/5068 ,  G06F2217/12 ,  H03K19/0033 ,  H03K19/00338 ,  H03K19/20 ,  Y02P90/265

摘要： This invention comprises a layout method to effectively protect logic circuits against soft errors (non-destructive errors) and circuit cells, with layout, which are protected against soft errors. In particular, the method protects against cases where multiple nodes in circuit are affected by a single event. These events lead to multiple errors in the circuit, and while several methods exist to deal with single node errors, multiple node errors are very hard to deal with using any currently existing protection methods. The method is particularly useful for CMOS based logic circuits in modern technologies (.ltoreq.90 nm), where the occurrence of multiple node pulses becomes high (due to the high integration level). It uses a unique layout configuration, which makes the circuits protected against single event generated soft-errors.

摘要翻译： 本发明包括一种有效保护逻辑电路免受软错误（非破坏性错误）和电路单元的布局方法，其布局具有防止软错误的布局。 特别地，该方法防止电路中的多个节点受单个事件影响的情况。 这些事件导致电路中的多个错误，并且虽然存在用于处理单节点错误的几种方法，但是多个节点错误很难处理使用任何当前存在的保护方法。 该方法对于现代技术（.ltoreq.90nm）中的基于CMOS的逻辑电路特别有用，其中多个节点脉冲的发生变高（由于高集成度）。 它使用独特的布局配置，这使得电路可以防止单个事件产生的软错误。