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公开(公告)号：US20050086624A1
公开(公告)日：2005-04-21
申请号：US10688460
申请日：2003-10-17
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： Objects are assigned to points in a rectangle by dividing the rectangle is divided into a plurality of smaller rectangles and applying an object assignment procedure, such as Kuhn's algorithm, to initially assigned objects in each second rectangle. The initial assignment is performed by calculating a maximal cost of assignment of objects to points, and selecting an assignment of objects having a minimum value of maximal cost, identified by iteratively recalculating the maximal matching assignment based on a midpoint of between the minimum and maximum costs.
摘要翻译： 通过将矩形划分为多个较小的矩形并将对象分配过程（例如Kuhn算法）应用于每个第二矩形中的初始分配对象，将对象分配给矩形中的点。 通过计算对象到点的分配的最大成本并且选择具有最大成本的最小值的对象的分配来执行初始分配，通过基于最小和最大成本之间的中点迭代地重新计算最大匹配分配来识别 。
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12.发明授权Multimode delay analysis for simplifying integrated circuit design timing models 失效用于简化集成电路设计时序模型的多模延迟分析公开(公告)号：US07512918B2
公开(公告)日：2009-03-31
申请号：US11205365
申请日：2005-08-17
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method of analyzing multimode delay in an integrated circuit design to produce a timing model for the integrated circuit design, by inputting a net list, IO arc delays, interconnection arc delays, and constant nets with assigned Boolean functions for the integrated circuit design, propagating the constant nets and assigning Boolean conditions to the IO arc delays and the interconnection arc delays, evaluating timing path delays and conditions for the integrated circuit design, creating the integrated circuit design timing model parameters, and outputting the integrated circuit design timing model. The method is especially desirable for netlists with very complicated mixing logics that include muxing of clocks. In particular, RRAMs are such netlists.
摘要翻译： 一种分析集成电路设计中的多模延迟的方法，通过输入集成电路设计的网络列表，IO弧延迟，互连电弧延迟和具有分配布尔函数的恒定网络来生成集成电路设计的定时模型，传播 恒定网络和布尔条件给IO弧延迟和互连电弧延迟，评估集成电路设计的定时路径延迟和条件，创建集成电路设计时序模型参数，并输出集成电路设计时序模型。 该方法对于具有非常复杂的混合逻辑（包括时钟复用）的网表来说是特别需要的。 特别地，RRAM是这样的网表。
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公开(公告)号：US20060117281A1
公开(公告)日：2006-06-01
申请号：US10999468
申请日：2004-11-30
CPC分类号： G06F17/5022
摘要： The present invention provides a method of verification of a RRAM tiling netlist. The method may include steps as follows. Properties “memory_number”, “clock_number” and “netlist_part” of all nets and cells of a RRAM tiling netlist are set to a value 0. A boolean function 0 is assigned to all ground nets of the RRAM tiling netlist, and a boolean function 1 is assigned to all power nets of the RRAM tiling netlist. The RRAM tiling netlist is verified for each customer memory Memk, k=1, 2, . . . , N.
摘要翻译： 本发明提供了一种RRAM拼接网表的验证方法。 该方法可以包括以下步骤。 属性RRAM平铺网表的所有网络和单元的“memory_number”，“clock_number”和“netlist_part”被设置为值0。 布尔函数0被分配给RRAM平铺网表的所有接地网，并且布尔函数1被分配给RRAM平铺网表的所有电网。 对于每个客户存储器验证RRAM平铺网表，其中k = 1,2，...。 。 。 ，N.
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14.发明申请Method and system for outputting a sequence of commands and data described by a flowchart 失效用于输出由流程图描述的命令和数据序列的方法和系统公开(公告)号：US20060020927A1
公开(公告)日：2006-01-26
申请号：US10894781
申请日：2004-07-20
IPC分类号： G06F9/45
CPC分类号： G06F17/5054
摘要： The present invention is a method and system for outputting a sequence of commands and data described by a flowchart. In an exemplary aspect of the present invention, a method for outputting a sequence of commands and data described by a flowchart includes steps as follows. A flowchart describing a sequence of commands and data is received. The flowchart includes a plurality of flowchart symbols. Each of the plurality of flowchart symbols is assigned a ROM (read only memory) record. Assigned ROM records are stored in a ROM. A module (e.g., a CKD, or the like) is generated to include the ROM, wherein the module receives as input a CLOCK signal, a RESET signal, an ENABLE signal and N binary inputs x1, x2, . . . xN, and outputs the sequence of commands and data.
摘要翻译： 本发明是用于输出由流程图描述的命令和数据序列的方法和系统。 在本发明的一个示例性方面，用于输出由流程图描述的命令和数据序列的方法包括以下步骤。 接收描述命令和数据序列的流程图。 流程图包括多个流程图符号。 多个流程图符号中的每一个被分配有ROM（只读存储器）记录。 分配的ROM记录存储在ROM中。 生成模块（例如，CKD等）以包括ROM，其中模块接收CLOCK信号，RESET信号，ENABLE信号和N个二进制输入x 1， x 2，...， 。 。 并且输出命令和数据的序列。
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公开(公告)号：US20060010092A1
公开(公告)日：2006-01-12
申请号：US10875128
申请日：2004-06-23
CPC分类号： G06F17/5045 , G06F12/0292 , G06Q10/0875 , G06Q99/00
摘要： A user-defined memory design is mapped to memories of a base platform for an IC that contains a plurality of memory sets, each containing a plurality of memories of a predetermined type. An optimal memory set is selected from the plurality of memory sets for the design by selecting a preference rate for each memory set from the plurality of sets based on the design and its connections to portions of the IC, and selectively assigning the design to one of the memory sets based on the preference rate. The design is optimally mapped to a plurality of memories of the selected memory set by defining an index of the position of each customer memory in the selected memory set. The customer memories in the selected memory set are arranged in an order, and successive numbers of memories of the selected memory set are assigned to each customer memory in order.
摘要翻译： 用户定义的存储器设计被映射到用于IC的基础平台的存储器，该存储器包含多个存储器组，每个存储器组包含预定类型的多个存储器。 从设计的多个存储器集合中选择最佳存储器集合，其基于设计及其与IC的部分的连接，从多个集合中选择每个存储器组的偏好率，并且将该设计选择性地分配给 基于优先级的内存集。 通过定义所选择的存储器组中的每个顾客存储器的位置的索引，将设计最佳地映射到所选存储器组的多个存储器。 所选择的存储器组中的客户存储器按顺序排列，并且所选择的存储器组的连续数量的存储器按顺序分配给每个客户存储器。
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16.发明申请Method for evaluating logic functions by logic circuits having optimized number of and/or switches 失效用于通过具有优化的数量和/或开关的逻辑电路来评估逻辑功能的方法公开(公告)号：US20050149302A1
公开(公告)日：2005-07-07
申请号：US11055752
申请日：2005-02-10
申请人： Andrey Nikitin , Alexander Andreev
发明人： Andrey Nikitin , Alexander Andreev
CPC分类号： G06F17/505
摘要： A method for creating a logic circuit with an optimized number of AND/OR switches, which evaluates a logic function defined in a high-level description. Through analyzing the dependency relationship among operators used to define the logic function, the present invention may simplify the functional steps used in the high-level description to define the logic function and thus create a logic circuit with an optimized number of AND/OR switches.
摘要翻译： 一种用于创建具有优化数量的AND / OR开关的逻辑电路的方法，其评估在高级描述中定义的逻辑功能。 通过分析用于定义逻辑功能的运算符之间的依赖关系，本发明可以简化用于定义逻辑功能的高级描述中使用的功能步骤，从而创建具有优化数量的AND / OR开关的逻辑电路。
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17.发明申请Parallel processor language, method for translating C++ programs into this language, and method for optimizing execution time of parallel processor programs 失效并行处理器语言，将C ++程序转换成该语言的方法，以及优化并行处理器程序执行时间的方法公开(公告)号：US20050066321A1
公开(公告)日：2005-03-24
申请号：US10667812
申请日：2003-09-22
申请人： Andrey Nikitin , Alexander Andreev
发明人： Andrey Nikitin , Alexander Andreev
摘要： The present invention is directed to a parallel processor language, a method for translating C++ programs into a parallel processor language, and a method for optimizing execution time of a parallel processor program. In an exemplary aspect of the present invention, a parallel processor program for defining a processor integrated circuit includes a plurality of processor commands with addresses. The plurality of processor commands may includes a starting processor command, and each of the plurality of processor commands includes one or more subcommands. When the processor integrated circuit executes the parallel processor program, the processor integrated circuit executes the staring processor command first and then executes the rest of the plurality of processor commands based on an order of the addresses. Moreover, when the processor integrated circuit executes a parallel processor command, the processor integrated circuit executes all subcommands included in the parallel processor command in parallel in one clock cycle.
摘要翻译： 本发明涉及并行处理器语言，用于将C ++程序转换为并行处理器语言的方法以及用于优化并行处理器程序的执行时间的方法。 在本发明的示例性方面，用于定义处理器集成电路的并行处理器程序包括具有地址的多个处理器命令。 多个处理器命令可以包括起始处理器命令，并且多个处理器命令中的每一个包括一个或多个子命令。 当处理器集成电路执行并行处理器程序时，处理器集成电路首先执行起始处理器命令，然后基于地址的顺序执行多个处理器命令中的其余部分。 此外，当处理器集成电路执行并行处理器命令时，处理器集成电路在一个时钟周期内并行地执行并行处理器命令中包括的所有子命令。
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18.发明申请公开(公告)号：US20050013155A1
公开(公告)日：2005-01-20
申请号：US10621737
申请日：2003-07-17
申请人： Andrey Nikitin , Alexander Andreev
发明人： Andrey Nikitin , Alexander Andreev
CPC分类号： G06F17/5022
摘要： The present invention is directed to a method and apparatus of IC implementation based on a C++ language description. In an exemplary aspect of the present invention, a method for evaluating a C++ description by an IC includes the following steps. First, a C++ description including a C++ program is provided. Then, the C++ program is stored in a first memory module (e.g., a ROM, or the like) of an IC. Next, a scalar input and/or an input array may be provided to the IC. Then, the C++ program may be executed by a control device module of the IC. Next, a scalar output and/or an output array may be read from the IC.
摘要翻译： 本发明涉及基于C ++语言描述的IC实现的方法和装置。 在本发明的一个示例性方面，用于通过IC评估C ++描述的方法包括以下步骤。 首先，提供包括C ++程序的C ++描述。 然后，C ++程序被存储在IC的第一存储器模块（例如，ROM等中）中。 接下来，可以向IC提供标量输入和/或输入阵列。 然后，C ++程序可以由IC的控制装置模块执行。 接下来，可以从IC读取标量输出和/或输出阵列。
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公开(公告)号：US07356743B2
公开(公告)日：2008-04-08
申请号：US11256829
申请日：2005-10-24
IPC分类号： G11C29/00
CPC分类号： G11C29/12 , G11C29/16 , G11C2029/1208
摘要： An RRAM design having linear BIST memory and rectangular BIST memory, the improvement comprising at least one of the linear BIST memory and the rectangular BIST memory formed only of flipflops and logic cells.
摘要翻译： 具有线性BIST存储器和矩形BIST存储器的RRAM设计，改进包括仅由触发器和逻辑单元形成的线性BIST存储器和矩形BIST存储器中的至少一个。
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公开(公告)号：US20070091702A1
公开(公告)日：2007-04-26
申请号：US11256829
申请日：2005-10-24
申请人： Andrey Nikitin , Ilya Neznanov , Alexander Andreev
发明人： Andrey Nikitin , Ilya Neznanov , Alexander Andreev
IPC分类号： G11C7/02
CPC分类号： G11C29/12 , G11C29/16 , G11C2029/1208
摘要： An RRAM design having linear BIST memory and rectangular BIST memory, the improvement comprising at least one of the linear BIST memory and the rectangular BIST memory formed only of flipflops and logic cells.
摘要翻译： 具有线性BIST存储器和矩形BIST存储器的RRAM设计，改进包括仅由触发器和逻辑单元形成的线性BIST存储器和矩形BIST存储器中的至少一个。
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