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1.发明申请Method and system for outputting a sequence of commands and data described by a flowchart 有权用于输出由流程图描述的命令和数据序列的方法和系统公开(公告)号：US20070169009A1
公开(公告)日：2007-07-19
申请号：US11260517
申请日：2005-10-27
IPC分类号： G06F9/45
CPC分类号： G06F8/66
摘要： The present invention is a method and system for outputting a sequence of commands and data described by a flowchart. The method includes steps as follows. A flowchart describing a sequence of commands and data is received. The flowchart includes a plurality of flowchart symbols. Each of the plurality of flowchart symbols is assigned a ROM (read only memory) record. Assigned ROM records are stored in a ROM. A processor is generated to include the ROM, wherein the processor receives as input a CLOCK signal, a RESET signal, an ENABLE signal and N binary inputs x1, x2, . . . xN, and outputs the sequence of commands and data.
摘要翻译： 本发明是用于输出由流程图描述的命令和数据序列的方法和系统。 该方法包括以下步骤。 接收描述命令和数据序列的流程图。 流程图包括多个流程图符号。 多个流程图符号中的每一个被分配有ROM（只读存储器）记录。 分配的ROM记录存储在ROM中。 产生处理器以包括ROM，其中处理器接收CLOCK信号，RESET信号，ENABLE信号和N个二进制输入x 1，x 2， 。 。 。 并且输出命令和数据的序列。
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公开(公告)号：US20050086624A1
公开(公告)日：2005-04-21
申请号：US10688460
申请日：2003-10-17
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： Objects are assigned to points in a rectangle by dividing the rectangle is divided into a plurality of smaller rectangles and applying an object assignment procedure, such as Kuhn's algorithm, to initially assigned objects in each second rectangle. The initial assignment is performed by calculating a maximal cost of assignment of objects to points, and selecting an assignment of objects having a minimum value of maximal cost, identified by iteratively recalculating the maximal matching assignment based on a midpoint of between the minimum and maximum costs.
摘要翻译： 通过将矩形划分为多个较小的矩形并将对象分配过程（例如Kuhn算法）应用于每个第二矩形中的初始分配对象，将对象分配给矩形中的点。 通过计算对象到点的分配的最大成本并且选择具有最大成本的最小值的对象的分配来执行初始分配，通过基于最小和最大成本之间的中点迭代地重新计算最大匹配分配来识别 。
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公开(公告)号：US20070044053A1
公开(公告)日：2007-02-22
申请号：US11205365
申请日：2005-08-17
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method of analyzing multimode delay in an integrated circuit design to produce a timing model for the integrated circuit design, by inputting a net list, IO arc delays, interconnection arc delays, and constant nets with assigned Boolean functions for the integrated circuit design, propagating the constant nets and assigning Boolean conditions to the IO arc delays and the interconnection arc delays, evaluating timing path delays and conditions for the integrated circuit design, creating the integrated circuit design timing model parameters, and outputting the integrated circuit design timing model. The method is especially desirable for netlists with very complicated mixing logics that include muxing of clocks. In particular, RRAMs are such netlists.
摘要翻译： 一种分析集成电路设计中的多模延迟的方法，通过输入集成电路设计的网络列表，IO弧延迟，互连电弧延迟和具有分配布尔函数的恒定网络来生成集成电路设计的定时模型，传播 恒定网络和布尔条件给IO弧延迟和互连电弧延迟，评估集成电路设计的定时路径延迟和条件，创建集成电路设计时序模型参数，并输出集成电路设计时序模型。 该方法对于具有非常复杂的混合逻辑（包括时钟复用）的网表来说是特别需要的。 特别地，RRAM是这样的网表。
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4.发明授权Multimode delay analysis for simplifying integrated circuit design timing models 失效用于简化集成电路设计时序模型的多模延迟分析公开(公告)号：US07512918B2
公开(公告)日：2009-03-31
申请号：US11205365
申请日：2005-08-17
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method of analyzing multimode delay in an integrated circuit design to produce a timing model for the integrated circuit design, by inputting a net list, IO arc delays, interconnection arc delays, and constant nets with assigned Boolean functions for the integrated circuit design, propagating the constant nets and assigning Boolean conditions to the IO arc delays and the interconnection arc delays, evaluating timing path delays and conditions for the integrated circuit design, creating the integrated circuit design timing model parameters, and outputting the integrated circuit design timing model. The method is especially desirable for netlists with very complicated mixing logics that include muxing of clocks. In particular, RRAMs are such netlists.
摘要翻译： 一种分析集成电路设计中的多模延迟的方法，通过输入集成电路设计的网络列表，IO弧延迟，互连电弧延迟和具有分配布尔函数的恒定网络来生成集成电路设计的定时模型，传播 恒定网络和布尔条件给IO弧延迟和互连电弧延迟，评估集成电路设计的定时路径延迟和条件，创建集成电路设计时序模型参数，并输出集成电路设计时序模型。 该方法对于具有非常复杂的混合逻辑（包括时钟复用）的网表来说是特别需要的。 特别地，RRAM是这样的网表。
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公开(公告)号：US20060117281A1
公开(公告)日：2006-06-01
申请号：US10999468
申请日：2004-11-30
CPC分类号： G06F17/5022
摘要： The present invention provides a method of verification of a RRAM tiling netlist. The method may include steps as follows. Properties “memory_number”, “clock_number” and “netlist_part” of all nets and cells of a RRAM tiling netlist are set to a value 0. A boolean function 0 is assigned to all ground nets of the RRAM tiling netlist, and a boolean function 1 is assigned to all power nets of the RRAM tiling netlist. The RRAM tiling netlist is verified for each customer memory Memk, k=1, 2, . . . , N.
摘要翻译： 本发明提供了一种RRAM拼接网表的验证方法。 该方法可以包括以下步骤。 属性RRAM平铺网表的所有网络和单元的“memory_number”，“clock_number”和“netlist_part”被设置为值0。 布尔函数0被分配给RRAM平铺网表的所有接地网，并且布尔函数1被分配给RRAM平铺网表的所有电网。 对于每个客户存储器验证RRAM平铺网表，其中k = 1,2，...。 。 。 ，N.
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6.发明申请Method and system for outputting a sequence of commands and data described by a flowchart 失效用于输出由流程图描述的命令和数据序列的方法和系统公开(公告)号：US20060020927A1
公开(公告)日：2006-01-26
申请号：US10894781
申请日：2004-07-20
IPC分类号： G06F9/45
CPC分类号： G06F17/5054
摘要： The present invention is a method and system for outputting a sequence of commands and data described by a flowchart. In an exemplary aspect of the present invention, a method for outputting a sequence of commands and data described by a flowchart includes steps as follows. A flowchart describing a sequence of commands and data is received. The flowchart includes a plurality of flowchart symbols. Each of the plurality of flowchart symbols is assigned a ROM (read only memory) record. Assigned ROM records are stored in a ROM. A module (e.g., a CKD, or the like) is generated to include the ROM, wherein the module receives as input a CLOCK signal, a RESET signal, an ENABLE signal and N binary inputs x1, x2, . . . xN, and outputs the sequence of commands and data.
摘要翻译： 本发明是用于输出由流程图描述的命令和数据序列的方法和系统。 在本发明的一个示例性方面，用于输出由流程图描述的命令和数据序列的方法包括以下步骤。 接收描述命令和数据序列的流程图。 流程图包括多个流程图符号。 多个流程图符号中的每一个被分配有ROM（只读存储器）记录。 分配的ROM记录存储在ROM中。 生成模块（例如，CKD等）以包括ROM，其中模块接收CLOCK信号，RESET信号，ENABLE信号和N个二进制输入x 1， x 2，...， 。 。 并且输出命令和数据的序列。
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公开(公告)号：US20060010092A1
公开(公告)日：2006-01-12
申请号：US10875128
申请日：2004-06-23
CPC分类号： G06F17/5045 , G06F12/0292 , G06Q10/0875 , G06Q99/00
摘要： A user-defined memory design is mapped to memories of a base platform for an IC that contains a plurality of memory sets, each containing a plurality of memories of a predetermined type. An optimal memory set is selected from the plurality of memory sets for the design by selecting a preference rate for each memory set from the plurality of sets based on the design and its connections to portions of the IC, and selectively assigning the design to one of the memory sets based on the preference rate. The design is optimally mapped to a plurality of memories of the selected memory set by defining an index of the position of each customer memory in the selected memory set. The customer memories in the selected memory set are arranged in an order, and successive numbers of memories of the selected memory set are assigned to each customer memory in order.
摘要翻译： 用户定义的存储器设计被映射到用于IC的基础平台的存储器，该存储器包含多个存储器组，每个存储器组包含预定类型的多个存储器。 从设计的多个存储器集合中选择最佳存储器集合，其基于设计及其与IC的部分的连接，从多个集合中选择每个存储器组的偏好率，并且将该设计选择性地分配给 基于优先级的内存集。 通过定义所选择的存储器组中的每个顾客存储器的位置的索引，将设计最佳地映射到所选存储器组的多个存储器。 所选择的存储器组中的客户存储器按顺序排列，并且所选择的存储器组的连续数量的存储器按顺序分配给每个客户存储器。
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公开(公告)号：US06587990B1
公开(公告)日：2003-07-01
申请号：US09678201
申请日：2000-10-01
IPC分类号： G06F1750
CPC分类号： G06F17/505
摘要： The present invention is a method and apparatus for optimizing the design of a combinational circuit. The method includes constructing a circuit sheaf for the combinational circuit and then performing vector optimization with domination. In the preferred embodiment, a complete BDD B is determined and, from that, a list of F-sets is computed. If the combinational circuit includes cells other than NOT, AND and XOR cells, the circuit is first transformed such that it only has those types of cells.
摘要翻译： 本发明是一种优化组合电路设计的方法和装置。 该方法包括为组合电路构建电路束，然后进行矢量优化。 在优选实施例中，确定完整的BDD B，并且从中计算出F组的列表。 如果组合电路包括除NOT，AND和XOR单元以外的单元，则首先对电路进行转换，使其仅具有这些类型的单元。
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公开(公告)号：US08735857B2
公开(公告)日：2014-05-27
申请号：US13271679
申请日：2011-10-12
CPC分类号： H03K19/17728 , H03K19/17796
摘要： A via-configurable circuit block may contain chains of p-type and n-type transistors that may or may not be interconnected by means of configurable vias. Configurable vias may also be used to connect various transistor terminals to a ground line, a power line and/or to various terminals that may provide connections outside of the circuit block.
摘要翻译： 通孔可配置电路块可以包含可以或可以不通过可配置通孔互连的p型和n型晶体管链。 可配置的通孔也可用于将各种晶体管端子连接到接地线，电力线和/或可提供电路块外部的连接的各种端子。
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公开(公告)号：US07739471B2
公开(公告)日：2010-06-15
申请号：US11256830
申请日：2005-10-24
IPC分类号： G06F12/02
CPC分类号： G11C8/12 , G11C2207/104
摘要： A method of configuring a random access memory matrix containing partially configured memories in the matrix. The method includes the steps of independently calculating a memory enable signal and a configuration signal for a partially configured memory in each memory tile of the memory matrix. Memory tiles not supported by a memory compiler are determined. A memory wrapper is provided for each tile not supported by the memory compiler. An address controller is inserted in the memory matrix for each tile in a group of tiles. Output signals from each memory location in a memory group having a common group index are combined into a single output signal. A first stripe of memory tiles containing non-configured memory having a first width is selected. A second strip of memory tiles containing configured memory having a second width is also selected.
摘要翻译： 一种在矩阵中配置包含部分配置的存储器的随机存取存储器矩阵的方法。 该方法包括以下步骤：对存储器矩阵的每个存储器块中的部分配置的存储器独立地计算存储器使能信号和配置信号。 确定内存编译器不支持的内存片。 为存储器编译器不支持的每个片提供内存包装器。 在一组瓦片中的每个瓦片的存储矩阵中插入地址控制器。 来自具有公共组索引的存储器组中的每个存储器位置的输出信号被组合成单个输出信号。 选择包含具有第一宽度的非配置存储器的第一条存储器片。 还选择包含具有第二宽度的配置存储器的第二条存储器片。
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