公开(公告)号：US20150039860A1

公开(公告)日：2015-02-05

申请号：US13955847

申请日：2013-07-31

Applicant: Apple Inc.

Inventor： Shyam Sundar ,  Conrado Blasco-Allue

IPC: G06F9/30

CPC classification number: G06F9/30032 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3863

Abstract: A system and method for efficiently performing microarchitectural checkpointing. A register rename unit within a processor determines whether a physical register number qualifies to have duplicate mappings. Information for maintenance of the duplicate mappings is stored in a register duplicate array (RDA). To reduce the penalty for misspeculation or exception recovery, control logic in the processor supports multiple checkpoints. The RDA is one of multiple data structures to have checkpoint copies of state. The RDA utilizes a content addressable memory (CAM) to store physical register numbers. The duplicate counts for both the current state and the checkpoint copies for a given physical register number are updated when instructions utilizing the given physical register number are retired. To reduce on-die real estate and power consumption, a single CAM entry is stores the physical register number and the other fields are stored in separate storage elements.

Abstract translation: 一种有效执行微架构检查点的系统和方法。 处理器内的寄存器重命名单元确定物理寄存器号码是否有资格具有重复的映射。 用于维护重复映射的信息存储在寄存器重复数组（RDA）中。 为了减少错误或异常恢复的处罚，处理器中的控制逻辑支持多个检查点。 RDA是具有状态检查点副本的多个数据结构之一。 RDA利用内容可寻址存储器（CAM）来存储物理寄存器编号。 对于给定的物理寄存器号码的当前状态和检查点副本的重复计数将在使用给定物理寄存器号码的指令退出时更新。 为了降低裸片上的不动产和功耗，单个CAM条目存储物理寄存器号，其他字段存储在单独的存储元件中。

公开(公告)号：US20140344558A1

公开(公告)日：2014-11-20

申请号：US13893898

申请日：2013-05-14

Applicant: Apple Inc.

Inventor： Douglas C. Holman ,  Ramesh B. Gunna ,  Conrado Blasco-Allue

IPC: G06F9/38

CPC classification number: G06F9/3806 ,  G06F9/30054 ,  G06F9/382 ,  G06F9/3848

Abstract: A system and method for efficient branch prediction. A processor includes a next fetch predictor to generate a fast branch prediction for branch instructions at an early pipeline stage. The processor also includes a main return address stack (RAS) at a later pipeline stage for predicting the target of return instructions. When a return instruction is encountered, the prediction from the next fetch predictor is replaced by the top of the main RAS. If there are any recent call or return instructions in flight toward the main RAS, then a separate prediction is generated by a mini-RAS.

Abstract translation: 一种有效的分支预测的系统和方法。 处理器包括下一个提取预测器，用于在早期流水线阶段生成分支指令的快速分支预测。 该处理器还包括在稍后流水线阶段的主返回地址堆栈（RAS），用于预测返回指令的目标。 当遇到返回指令时，来自下一个提取预测器的预测由主RAS的顶部代替。 如果飞行中有最近的呼叫或返回指令进入主RAS，则由小型RAS产生单独的预测。

公开(公告)号：US20140215188A1

公开(公告)日：2014-07-31

申请号：US13749999

申请日：2013-01-25

Applicant: APPLE INC.

Inventor： John H. Mylius ,  Gerard R. Williams, III ,  Shyam Sundar Balasubramanian ,  Conrado Blasco-Allue

IPC: G06F9/30

CPC classification number: G06F9/3836 ,  G06F9/30145 ,  G06F9/4881 ,  G06F9/4887

Abstract: In an embodiment, a processor includes a multi-level dispatch circuit configured to supply operations for execution by multiple parallel execution pipelines. The multi-level dispatch circuit may include multiple dispatch buffers, each of which is coupled to multiple reservation stations. Each reservation station may be coupled to a respective execution pipeline and may be configured to schedule instruction operations (ops) for execution in the respective execution pipeline. The sets of reservation stations coupled to each dispatch buffer may be non-overlapping. Thus, if a given op is to be executed in a given execution pipeline, the op may be sent to the dispatch buffer which is coupled to the reservation station that provides ops to the given execution pipeline.

Abstract translation: 在一个实施例中，处理器包括被配置为提供由多个并行执行管线执行的操作的多级调度电路。 多级调度电路可以包括多个调度缓冲器，每个调度缓冲器耦合到多个保留站。 每个保留站可以耦合到相应的执行流水线，并且可以被配置为调度用于在相应的执行流水线中执行的指令操作（op）。 耦合到每个调度缓冲器的保留站组可以是不重叠的。 因此，如果在给定的执行流水线中执行给定的操作，则操作可以被发送到调度缓冲器，该调度缓冲器耦合到向给定的执行流水线提供操作的保留站。

公开(公告)号：US20140208073A1

公开(公告)日：2014-07-24

申请号：US13747977

申请日：2013-01-23

Applicant: APPLE INC.

Inventor： Conrado Blasco-Allue ,  Sandeep Gupta

IPC: G06F9/30

CPC classification number: G06F9/30058 ,  G06F9/3001 ,  G06F9/30094 ,  G06F9/30145 ,  G06F9/3804

Abstract: A processor and method for fusing together an arithmetic instruction and a branch instruction. The processor includes an instruction fetch unit configured to fetch instructions. The processor may also include an instruction decode unit that may be configured to decode the fetched instructions into micro-operations for execution by an execution unit. The decode unit may be configured to detect an occurrence of an arithmetic instruction followed by a branch instruction in program order, wherein the branch instruction, upon execution, changes a program flow of control dependent upon a result of execution of the arithmetic instruction. In addition, the processor may further be configured to fuse together the arithmetic instruction and the branch instruction such that a single micro-operation is formed. The single micro-operation includes execution information based upon both the arithmetic instruction and the branch instruction.

Abstract translation: 一种用于将算术指令和分支指令融合在一起的处理器和方法。 处理器包括被配置为提取指令的指令获取单元。 处理器还可以包括指令解码单元，其可被配置为将获取的指令解码为微执行以由执行单元执行。 解码单元可以被配置为以程序顺序检测随后是分支指令的算术指令的发生，其中分支指令在执行时根据算术指令的执行结果改变程序控制流程。 此外，处理器还可以被配置为将算术指令和分支指令融合在一起，使得形成单个微操作。 单个微操作包括基于算术指令和分支指令的执行信息。