公开(公告)号：US09626185B2

公开(公告)日：2017-04-18

申请号：US13774093

申请日：2013-02-22

申请人： Apple Inc.

发明人： Shyam Sundar ,  Ian D. Kountanis ,  Conrado Blasco-Allue ,  Gerard R. Williams, III ,  Wei-Han Lien ,  Ramesh B. Gunna

IPC分类号： G06F15/00 ,  G06F9/30 ,  G06F9/40 ,  G06F9/38

CPC分类号： G06F9/30054 ,  G06F9/30181 ,  G06F9/382 ,  G06F9/3842 ,  G06F9/3844

摘要： Various techniques for processing and pre-decoding branches within an IT instruction block. Instructions are fetched and cached in an instruction cache, and pre-decode bits are generated to indicate the presence of an IT instruction and the likely boundaries of the IT instruction block. If an unconditional branch is detected within the likely boundaries of an IT instruction block, the unconditional branch is treated as if it were a conditional branch. The unconditional branch is sent to the branch direction predictor and the predictor generates a branch direction prediction for the unconditional branch.

公开(公告)号：US20160026463A1

公开(公告)日：2016-01-28

申请号：US14444798

申请日：2014-07-28

申请人： Apple Inc.

发明人： Shyam Sundar

IPC分类号： G06F9/30 ,  G06F9/38

摘要： A system and method for reducing the latency of data move operations. A register rename unit within a processor determines whether a decoded move instruction qualifies for a zero cycle move operation. If so, control logic assigns a physical register identifier associated with a source operand of the move instruction to the destination operand of the move instruction. Additionally, the register rename unit marks the given move instruction to prevent it from proceeding in the processor pipeline. Further maintenance of the particular physical register identifier may be done by the register rename unit during commit of the given move instruction.

摘要翻译： 一种用于减少数据移动操作的延迟的系统和方法。 处理器内的寄存器重命名单元确定解码的移动指令是否符合零周期移动操作。 如果是这样，则控制逻辑将与移动指令的源操作数相关联的物理寄存器标识分配给移动指令的目的地操作数。 此外，寄存器重命名单元标记给定的移动指令以防止其在处理器管线中继续进行。 特定物理寄存器标识符的进一步维护可以在给定移动指令的提交期间由寄存器重命名单元完成。

公开(公告)号：US10241557B2

公开(公告)日：2019-03-26

申请号：US14104042

申请日：2013-12-12

申请人： Apple Inc.

发明人： Conrado Blasco ,  Ronald P Hall ,  Ramesh B Gunna ,  Ian D Kountanis ,  Shyam Sundar ,  André Seznec

IPC分类号： G06F9/38 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3234 ,  G06F1/3296

摘要： A processor includes a mechanism for disabling a memory array of a branch prediction unit. The processor may include a next fetch prediction unit that may include a number of entries. Each entry may correspond to a next instruction fetch group and may store an indication of whether or not the corresponding the next fetch group includes a conditional branch instruction. In response to an indication that the next fetch group does not include a conditional branch instruction, the fetch prediction unit may be configured to disable, in a next instruction execution cycle, the memory array of the branch prediction unit.

公开(公告)号：US20160011875A1

公开(公告)日：2016-01-14

申请号：US14325981

申请日：2014-07-08

申请人： Apple Inc.

发明人： Shyam Sundar

IPC分类号： G06F9/38 ,  G06F12/08

CPC分类号： G06F9/3808 ,  G06F9/3812 ,  G06F12/0875 ,  G06F2212/452

摘要： A system and method for efficiently decoding and handling undefined instructions. A semiconductor chip predecodes instructions of a computer program. In response to determining a particular instruction is an undefined operation, the chip replaces an N-bit opcode in the particular instruction with an N-bit pattern different from the opcode. When instructions are fetched from an instruction cache, the corresponding opcodes are compared to the N-bit pattern. When a match is found, a trap may be set. The trap may later cause an exception handler subroutine for undefined operations to initiate execution.

摘要翻译： 一种有效解码和处理未定义指令的系统和方法。 半导体芯片预处理计算机程序的指令。 响应于确定特定指令是未定义的操作，芯片用与操作码不同的N位模式替换特定指令中的N位操作码。 当从指令高速缓存中取出指令时，将相应的操作码与N位模式进行比较。 当发现匹配时，可以设置陷阱。 陷阱可能会导致未定义操作的异常处理程序子程序启动执行。

公开(公告)号：US20140244976A1

公开(公告)日：2014-08-28

申请号：US13774093

申请日：2013-02-22

申请人： APPLE INC.

发明人： Shyam Sundar ,  Ian D. Kountanis ,  Conrado Blasco-Allue ,  Gerard R. Williams, III ,  Wei-Han Lien ,  Ramesh B. Gunna

IPC分类号： G06F9/30

CPC分类号： G06F9/30054 ,  G06F9/30181 ,  G06F9/382 ,  G06F9/3842 ,  G06F9/3844

摘要： Various techniques for processing and pre-decoding branches within an IT instruction block. Instructions are fetched and cached in an instruction cache, and pre-decode bits are generated to indicate the presence of an IT instruction and the likely boundaries of the IT instruction block. If an unconditional branch is detected within the likely boundaries of an IT instruction block, the unconditional branch is treated as if it were a conditional branch. The unconditional branch is sent to the branch direction predictor and the predictor generates a branch direction prediction for the unconditional branch.

摘要翻译： 用于在IT指令块内处理和预解码分支的各种技术。 指令被取出并缓存在指令高速缓存中，并且生成预解码位以指示IT指令的存在以及IT指令块的可能边界。 如果在IT指令块的可能边界内检测到无条件分支，则无条件分支被视为是条件分支。 无条件分支被发送到分支方向预测器，预测器产生无条件分支的分支方向预测。

公开(公告)号：US20140195789A1

公开(公告)日：2014-07-10

申请号：US13735694

申请日：2013-01-07

申请人： APPLE INC.

发明人： Sandeep Gupta ,  Shyam Sundar ,  Wei-Han Lien ,  Gerard R. Williams, III ,  Conrado Blasco-Allue

IPC分类号： G06F9/38

CPC分类号： G06F9/3844 ,  G06F9/30072 ,  G06F9/3806 ,  G06F9/3848

摘要： A circuit for implementing a branch target buffer. The branch target buffer may include a memory that stores a plurality of entries. Each entry may include a tag value, a target value, and a prediction accuracy value. A received index value corresponding to an indirect branch instruction may be used to select one of entries of the plurality of entries, and a received tag value may then be compared to the tag value of the selected entries in the memory. An entry in the memory may be selected in response to a determination that the received tag does not match the tag value of compared entries. The selected entry may be allocated to the indirect instruction branch dependent upon the prediction accuracy values of the plurality of entries.

摘要翻译： 用于实现分支目标缓冲器的电路。 分支目标缓冲器可以包括存储多个条目的存储器。 每个条目可以包括标签值，目标值和预测精度值。 对应于间接分支指令的接收到的索引值可以用于选择多个条目中的一个条目，然后将接收的标签值与存储器中所选条目的标签值进行比较。 响应于接收到的标签与被比较的条目的标签值不匹配的确定，可以选择存储器中的条目。 所选择的条目可以根据多个条目的预测精度值分配给间接指令分支。

公开(公告)号：US20140089638A1

公开(公告)日：2014-03-27

申请号：US13627884

申请日：2012-09-26

申请人： APPLE INC.

发明人： John H. Mylius ,  Gerard R. Williams III ,  James B. Keller ,  Fang Liu ,  Shyam Sundar

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3017 ,  G06F9/30138 ,  G06F9/3016 ,  G06F9/345 ,  G06F9/384 ,  G06F9/3861 ,  G06F9/3867

摘要： Various techniques for processing instructions that specify multiple destinations. A first portion of a processor pipeline is configured to split a multi-destination instruction into a plurality of single-destination operations. A second portion of the pipeline is configured to process the plurality of single-destination operations. A third portion of the pipeline is configured to merge the plurality of single-destination operations into one or more multi-destination operations. The one or more multi-destination operations may be performed. The first portion of the pipeline may include a decode unit. The second portion of the pipeline may include a map unit, which may in turn include circuitry configured to maintain a list of free architectural registers and a mapping table that maps physical registers to architectural registers. The third portion of the pipeline may comprise a dispatch unit. In some embodiments, this may provide certain advantages such as reduced area and/or power consumption.

摘要翻译： 用于处理指定多个目的地的指令的各种技术。 处理器流水线的第一部分被配置为将多目的地指令分割成多个单目的地操作。 流水线的第二部分被配置为处理多个单目的地操作。 流水线的第三部分被配置为将多个单目的地操作合并成一个或多个多目的地操作。 可以执行一个或多个多目的地操作。 流水线的第一部分可以包括解码单元。 流水线的第二部分可以包括地图单元，其可以依次包括被配置为维护空闲架构寄存器的列表的电路和将物理寄存器映射到架构寄存器的映射表。 管道的第三部分可以包括调度单元。 在一些实施例中，这可以提供某些优点，例如减小面积和/或功率消耗。

公开(公告)号：US10901484B2

公开(公告)日：2021-01-26

申请号：US16363517

申请日：2019-03-25

申请人： Apple Inc.

发明人： Conrado Blasco ,  Ronald P. Hall ,  Ramesh B. Gunna ,  Ian D. Kountanis ,  Shyam Sundar ,  André Seznec

IPC分类号： G06F9/38 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3234 ,  G06F1/3296

摘要： A processor includes a mechanism for disabling a memory array of a branch prediction unit. The processor may include a next fetch prediction unit that may include a number of entries. Each entry may correspond to a next instruction fetch group and may store an indication of whether or not the corresponding the next fetch group includes a conditional branch instruction. In response to an indication that the next fetch group does not include a conditional branch instruction, the fetch prediction unit may be configured to disable, in a next instruction execution cycle, the memory array of the branch prediction unit.

公开(公告)号：US09940262B2

公开(公告)日：2018-04-10

申请号：US14491149

申请日：2014-09-19

申请人： Apple Inc.

发明人： Shyam Sundar ,  Richard F. Russo ,  Ronald P. Hall ,  Conrado Blasco

IPC分类号： G06F12/1045 ,  G06F12/0875 ,  G06F9/38 ,  G06F9/32 ,  G06F12/1027

CPC分类号： G06F12/1045 ,  G06F9/324 ,  G06F9/3804 ,  G06F9/382 ,  G06F12/0875 ,  G06F12/1027 ,  G06F2212/452 ,  G06F2212/684

摘要： A system and method for efficiently indicating branch target addresses. A semiconductor chip predecodes instructions of a computer program prior to installing the instructions in an instruction cache. In response to determining a particular instruction is a control flow instruction with a displacement relative to a program counter address (PC), the chip replaces a portion of the PC relative displacement in the particular instruction with a subset of a target address. The subset of the target address is an untranslated physical subset of the full target address. When the recoded particular instruction is fetched and decoded, the remaining portion of the PC relative displacement is added to a virtual portion of the PC used to fetch the particular instruction. The result is concatenated with the portion of the target address embedded in the fetched particular instruction to form a full target address.

公开(公告)号：US09311100B2

公开(公告)日：2016-04-12

申请号：US13735694

申请日：2013-01-07

申请人： Apple Inc.

发明人： Sandeep Gupta ,  Shyam Sundar ,  Wei-Han Lien ,  Gerard R. Williams, III ,  Conrado Blasco-Allue

IPC分类号： G06F9/00 ,  G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3844 ,  G06F9/30072 ,  G06F9/3806 ,  G06F9/3848

摘要： A circuit for implementing a branch target buffer. The branch target buffer may include a memory that stores a plurality of entries. Each entry may include a tag value, a target value, and a prediction accuracy value. A received index value corresponding to an indirect branch instruction may be used to select one of entries of the plurality of entries, and a received tag value may then be compared to the tag value of the selected entries in the memory. An entry in the memory may be selected in response to a determination that the received tag does not match the tag value of compared entries. The selected entry may be allocated to the indirect instruction branch dependent upon the prediction accuracy values of the plurality of entries.

摘要翻译： 用于实现分支目标缓冲器的电路。 分支目标缓冲器可以包括存储多个条目的存储器。 每个条目可以包括标签值，目标值和预测精度值。 对应于间接分支指令的接收到的索引值可以用于选择多个条目中的一个条目，然后将接收到的标签值与存储器中所选条目的标签值进行比较。 响应于接收到的标签与被比较的条目的标签值不匹配的确定，可以选择存储器中的条目。 所选择的条目可以根据多个条目的预测精度值分配给间接指令分支。