公开(公告)号：US20230376252A1

公开(公告)日：2023-11-23

申请号：US18200544

申请日：2023-05-22

申请人： Intel Corporation

发明人： VEDVYAS SHANBHOGUE ,  JASON W. BRANDT ,  RAVI L. SAHITA ,  BARRY E. HUNTLEY ,  BAIJU V. PATEL

IPC分类号： G06F3/06 ,  G06F9/30 ,  G06F21/52 ,  G06F9/38 ,  G06F12/1009 ,  G06F12/109 ,  G06F12/1027 ,  G06F12/1081 ,  G06F12/1045 ,  G06F12/14 ,  G06F12/1036

CPC分类号： G06F3/0673 ,  G06F9/30145 ,  G06F3/0622 ,  G06F3/0629 ,  G06F21/52 ,  G06F9/3861 ,  G06F9/30054 ,  G06F9/3806 ,  G06F9/30134 ,  G06F12/1009 ,  G06F9/30101 ,  G06F12/109 ,  G06F12/1027 ,  G06F12/1081 ,  G06F12/1063 ,  G06F12/1491 ,  G06F12/1036 ,  G06F2212/651 ,  G06F2212/1052 ,  G06F2212/151 ,  G06F2212/657

摘要： A processor of an aspect includes a decode unit to decode an instruction. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the instruction, is to determine that an attempted change due to the instruction, to a shadow stack pointer of a shadow stack, would cause the shadow stack pointer to exceed an allowed range. The execution unit is also to take an exception in response to determining that the attempted change to the shadow stack pointer would cause the shadow stack pointer to exceed the allowed range. Other processors, methods, systems, and instructions are disclosed.

公开(公告)号：US20230195467A1

公开(公告)日：2023-06-22

申请号：US17556166

申请日：2021-12-20

申请人： Arm Limited

发明人： Houdhaifa BOUZGUARROU ,  Thibaut Elie LANOIS ,  Guillaume BOLBENES

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3844 ,  G06F9/3816 ,  G06F9/30054

摘要： A data processing apparatus is provided that includes bimodal control flow prediction circuitry for performing a prediction of whether a conditional control flow instruction will be taken. Storage circuitry stores, in association with the control flow instruction, a stored state of the data processing apparatus and reversal circuitry reverses the prediction in dependence on the stored state of the data processing apparatus corresponding with a current state of the data processing apparatus when execution of the control flow instruction is to be performed.

公开(公告)号：US20190205141A1

公开(公告)日：2019-07-04

申请号：US16298535

申请日：2019-03-11

申请人： Google LLC

发明人： Dong Hyuk Woo ,  Andrew Everett Phelps

IPC分类号： G06F9/355 ,  G06F9/38 ,  G06F9/345 ,  G06F9/30 ,  G06F17/16 ,  G06F9/32

CPC分类号： G06F9/355 ,  G06F9/3001 ,  G06F9/30036 ,  G06F9/30054 ,  G06F9/30061 ,  G06F9/30065 ,  G06F9/30101 ,  G06F9/325 ,  G06F9/3455 ,  G06F9/3555 ,  G06F9/3836 ,  G06F17/16 ,  G06F2212/454

摘要： Methods, systems, and apparatus, including an apparatus for processing an instruction for accessing a N-dimensional tensor, the apparatus including multiple tensor index elements and multiple dimension multiplier elements, where each of the dimension multiplier elements has a corresponding tensor index element. The apparatus includes one or more processors configured to obtain an instruction to access a particular element of a N-dimensional tensor, where the N-dimensional tensor has multiple elements arranged across each of the N dimensions, and where N is an integer that is equal to or greater than one; determine, using one or more tensor index elements of the multiple tensor index elements and one or more dimension multiplier elements of the multiple dimension multiplier elements, an address of the particular element; and output data indicating the determined address for accessing the particular element of the N-dimensional tensor.

公开(公告)号：US20180136934A1

公开(公告)日：2018-05-17

申请号：US15352517

申请日：2016-11-15

申请人： Andes Technology Corporation

发明人： Jen-Chih Tseng ,  Hong-Men Su ,  Chuan-Hua Chang

IPC分类号： G06F9/30 ,  G06F9/34

CPC分类号： G06F9/30054 ,  G06F9/322

摘要： A data processing system includes a control register, a program counter and a controller. The control register is used to store a level status of an execution flow and at least one return address. When the controller reads a block call instruction while a level status of the execution flow has an initial value, the controller stores a return address of the block call instruction in the control register, increments a value of the level status, and redirects the execution flow to a target address indicated by the block call instruction. When the controller reads a block return instruction and the value of the level status is not equal to the initial value, the controller decrements the value of the level status. If the value of the level status becomes equal to the initial value, the controller redirects the execution flow to the return address.

公开(公告)号：US09940137B2

公开(公告)日：2018-04-10

申请号：US15042306

申请日：2016-02-12

申请人： ARM LIMITED

发明人： Matthew Lee Winrow ,  Antony John Penton

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F12/0875

CPC分类号： G06F9/3802 ,  G06F9/30054 ,  G06F9/327 ,  G06F9/3804 ,  G06F9/3808 ,  G06F9/3861 ,  G06F12/0875 ,  G06F2212/452

摘要： Data processing apparatus comprises a processor configured to execute instructions, the processor having a pipelined instruction fetching unit configured to fetch instructions from memory during a pipeline period of two or more processor clock cycles prior to execution of those instructions by the processor; exception logic configured to respond to a detected processing exception having an exception type selected from a plurality of exception types, by storing a current processor status and diverting program flow to an exception address dependent upon the exception type so as to control the instruction fetching unit to initiate fetching of an exception instruction at the exception address; and an exception cache configured to cache information, for at least one of the exception types, relating to execution of the exception instruction at the exception address corresponding to that exception type and to provide the cached information to the processor in response to detection of an exception of that exception type.

公开(公告)号：US09940129B2

公开(公告)日：2018-04-10

申请号：US15087269

申请日：2016-03-31

申请人： Optimum Semiconductor Technologies, Inc.

发明人： Mayan Moudgill ,  Gary Nacer ,  C. John Glossner ,  A. Joseph Hoane ,  Paul Hurtley ,  Murugappan Senthilvelan ,  Pablo Balzola

IPC分类号： G06F12/08 ,  G06F9/30 ,  G06F3/06 ,  G06F12/0875 ,  G06F12/0893 ,  G06F12/1009 ,  G06F12/0862 ,  G06F9/32 ,  G06F9/355

CPC分类号： G06F9/30029 ,  G06F3/0604 ,  G06F3/0647 ,  G06F3/0673 ,  G06F9/30 ,  G06F9/30032 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30054 ,  G06F9/30058 ,  G06F9/3013 ,  G06F9/322 ,  G06F9/355 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0893 ,  G06F12/1009 ,  G06F2212/452 ,  G06F2212/60 ,  G06F2212/602

摘要： A computer processor with register direct branches and employing an instruction preload structure is disclosed. The computer processor may include a hierarchy of memories comprising a first memory organized in a structure having one or more entries for one or more addresses corresponding to one or more instructions. The one or more entries of the one or more addresses may have a starting address. The structure may have one or more locations for storing the one or more instructions. The computer processor may include one or more registers to which one or more corresponding instruction addresses are writable. The computer processor may include processing logic. In response to the processing logic writing the one or more instruction addresses to the one or more registers, the processing logic may to pre-fetch the one or more instructions of a linear sequence of instructions from a first memory level of the hierarchy of memories into a second memory level of the hierarchy of memories beginning at the starting address. At least one address of the one or more addresses may be the contents of a register of the one or more registers.

公开(公告)号：US20180032340A1

公开(公告)日：2018-02-01

申请号：US15662454

申请日：2017-07-28

申请人： Technische Universität München

发明人： Andreas Ibing ,  Julian Kirsch

IPC分类号： G06F9/30 ,  G06F9/32 ,  G06F9/45

CPC分类号： G06F9/30065 ,  G06F8/443 ,  G06F8/452 ,  G06F9/30054 ,  G06F9/325 ,  G06F11/0706 ,  G06F11/0751

摘要： Processor comprising an execution unit and a detection unit which are functionally connected, wherein the execution unit is configured to execute computer programs, and wherein the detection unit is configured to detect infinite loops during the execution of a computer program in the execution unit during run-time, wherein the computer program comprises a plurality of go-to instructions, wherein each go-to instruction is characterized by a corresponding branch address, wherein the detection unit is configured to calculate a detection function of the branch addresses of a branch sequence, the branch sequence comprising a sequence of executed go-to instructions, and wherein the detection function is chosen such that an increased value of the detection function is characteristic of an infinite loop in the branch sequence in which at least one go-to instruction is repeated.

公开(公告)号：US09875104B2

公开(公告)日：2018-01-23

申请号：US15014265

申请日：2016-02-03

申请人： Google Inc.

发明人： Dong Hyuk Woo ,  Andrew Everett Phelps

IPC分类号： G06F9/302 ,  G06F7/52 ,  G06F9/355 ,  G06F9/30 ,  G06F17/16 ,  G06F9/32

CPC分类号： G06F9/355 ,  G06F9/3001 ,  G06F9/30036 ,  G06F9/30054 ,  G06F9/30061 ,  G06F9/30065 ,  G06F9/30101 ,  G06F9/325 ,  G06F9/3455 ,  G06F9/3555 ,  G06F9/3836 ,  G06F17/16 ,  G06F2212/454

摘要： Methods, systems, and apparatus, including an apparatus for processing an instruction for accessing a N-dimensional tensor, the apparatus including multiple tensor index elements and multiple dimension multiplier elements, where each of the dimension multiplier elements has a corresponding tensor index element. The apparatus includes one or more processors configured to obtain an instruction to access a particular element of a N-dimensional tensor, where the N-dimensional tensor has multiple elements arranged across each of the N dimensions, and where N is an integer that is equal to or greater than one; determine, using one or more tensor index elements of the multiple tensor index elements and one or more dimension multiplier elements of the multiple dimension multiplier elements, an address of the particular element; and output data indicating the determined address for accessing the particular element of the N-dimensional tensor.

公开(公告)号：US20180004531A1

公开(公告)日：2018-01-04

申请号：US15199399

申请日：2016-06-30

申请人： Microsoft Technology Licensing, LLC

发明人： Ling Tony Chen ,  Kenneth D. Johnson ,  Jonathan E. Lange ,  Kinshumann ,  Matthew Miller ,  Neeraj Singh

IPC分类号： G06F9/38 ,  G06F3/06 ,  G06F9/30

CPC分类号： G06F9/3861 ,  G06F3/0604 ,  G06F3/0631 ,  G06F3/0673 ,  G06F9/30032 ,  G06F9/30054 ,  G06F11/28 ,  G06F21/6227

摘要： In one example, a method includes allocating separate portions of memory for a control stack and a data stack. The method also includes, upon detecting a call instruction, storing a first return address in the control stack and a second return address in the data stack; and upon detecting a return instruction, popping the first return address from the control stack and the second return address from the data stack and raising an exception if the two return addresses do not match. Otherwise, the return instruction returns the first return address. Additionally, the method includes executing an exception handler in response to the return instruction detecting an exception, wherein the exception handler is to pop one or more return addresses from the control stack until the return address on a top of the control stack matches the return address on a top of the data stack.

公开(公告)号：US20170344371A1

公开(公告)日：2017-11-30

申请号：US15165395

申请日：2016-05-26

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： JAMES J. BONANNO ,  MICHAEL J. CADIGAN, JR. ,  ADAM B. COLLURA ,  DANIEL LIPETZ ,  BRIAN R. PRASKY

IPC分类号： G06F9/30

CPC分类号： G06F9/30058 ,  G06F9/30021 ,  G06F9/30054 ,  G06F9/30134 ,  G06F9/30145 ,  G06F9/324 ,  G06F9/34 ,  G06F9/3806

摘要： Examples of techniques for distance-based branch prediction are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method includes: determining, by a processing system, a potential return instruction address (IA) by determining whether a relationship is satisfied between a first target IA and a first branch IA; storing a second branch IA as a return when a target IA of a second branch matches a potential return IA for the second branch; and applying the potential return IA for the second branch as a predicted target IA of a predicted branch IA stored as a return.