IMAGE FUSION ARCHITECTURE
    11.
    发明申请

    公开(公告)号:US20200302582A1

    公开(公告)日:2020-09-24

    申请号:US16358094

    申请日:2019-03-19

    Applicant: Apple Inc.

    Abstract: Embodiments relate to circuitry for performing fusion of two images captured with two different exposure times to generate a fused image having a higher dynamic range. Information about first keypoints is extracted from the first image by processing pixel values of pixels in the first image. A model describing correspondence between the first image and the second image is then built by processing at least the information about first keypoints. A processed version of the first image is warped using mapping information in the model to generate a warped version of the first image spatially more aligned to the second image than to the first image. The warped version of the first image is fused with a processed version of the second image to generate the fused image.

    ADJUSTING CONFIDENCE VALUES FOR CORRECTING PIXEL DEFECTS

    公开(公告)号:US20200053302A1

    公开(公告)日:2020-02-13

    申请号:US16101154

    申请日:2018-08-10

    Applicant: Apple Inc.

    Abstract: Embodiments relate to a pixel defect detection circuit for detecting and correcting defective pixels in captured image frames. The pixel defect detection circuit includes a defect pixel location table that maps pixel locations in an image frame to respective confidence values, each confidence value indicating a likelihood that a corresponding pixel is defective. The pixel defect detection circuit further includes a dynamic defect processing circuit configured to determine whether a first pixel of an image frame is defective, and a flatness detection circuit configured to determine whether the first pixel is in a flat region of the image frame. The confidence value corresponding to the location of the first pixel is updated based upon whether the first pixel is determined be defective if the first pixel is determined to be in a flat region, and not updated if the first pixel is determined to not be in a flat region.

    Correcting pixel defects based on defect history in an image processing pipeline

    公开(公告)号:US10440299B2

    公开(公告)日:2019-10-08

    申请号:US14845659

    申请日:2015-09-04

    Applicant: Apple Inc.

    Abstract: An image signal processor may include a pixel defect correction component that tracks defect history for frames captured by an image sensor and applies the history when identifying and correcting defective pixels in a frame. The component maintains a defect pixel location table that includes a defect confidence value for pixels of the image sensor. The component identifies defective pixels in a frame, for example by comparing each pixel's value to the values of its neighbor pixels. If a pixel is detected as defective, its defect confidence value may be incremented. Otherwise, the value may be decremented. If a pixel's defect confidence value is over a defect confidence threshold, the pixel is considered defective and thus may be corrected. If a pixel's defect confidence value is under the threshold, the pixel is considered not defective and thus may not be corrected even if the pixel was detected as defective.

    Sensor Cropped Video Image Stabilization (VIS)

    公开(公告)号:US20240098368A1

    公开(公告)日:2024-03-21

    申请号:US17933941

    申请日:2022-09-21

    Applicant: Apple Inc.

    CPC classification number: H04N5/23277 G06T7/38

    Abstract: Devices, methods, and non-transitory program storage devices are disclosed herein to perform predictive image sensor cropping operations to improve the performance of video image stabilization operations, especially for high resolution image sensors. According to some embodiments, the techniques include, for each of one or more respective images of a first plurality of images: obtaining image information corresponding to one or more images in the first plurality of images captured prior to the respective image; predicting, for the respective image, an image sensor cropping region to be read out from the first image sensor; and then reading out, into a memory, a first cropped version of the respective image comprising only the predicted image sensor cropping region for the respective image. Then, a first video may be produced based, at least in part, on the first cropped versions of the one or more respective images of the first plurality of images.

    Circuit For Combined Down Sampling And Correction Of Image Data

    公开(公告)号:US20240029198A1

    公开(公告)日:2024-01-25

    申请号:US18230560

    申请日:2023-08-04

    Applicant: Apple Inc.

    CPC classification number: G06T3/4007 H04N23/88

    Abstract: A foveated down sampling and correction (FDS-C) circuit for combined down sampling and correction of chromatic aberrations in images. The FDS-C circuit performs down sampling and interpolation of pixel values of a first subset of pixels of a color in a raw image using down sampling scale factors and first interpolation coefficients to generate first corrected pixel values for pixels of the color in a first corrected version of the raw image. The FDS-C circuit further performs interpolation of pixel values of a second subset of the pixels in the first corrected version using second interpolation coefficients to generate second corrected pixel values for pixels of the color in a second corrected version of the raw image. Pixels in the first subset are arranged in a first direction, pixels in the second subset are arranged in a second direction, and the down sampling scale factors vary along the first direction.

    Dual-mode image fusion architecture

    公开(公告)号:US11836889B2

    公开(公告)日:2023-12-05

    申请号:US17173049

    申请日:2021-02-10

    Applicant: Apple Inc.

    Abstract: Embodiments relate to an image processing circuit able to perform image fusion on received images in at least a first mode for fusing demosaiced and downscaled image data, and a second mode for fusing raw image data. Raw image data is received from an image sensor in Bayer RGB format. In the first mode, the raw image data is demosaiced and resampled prior to undergoing image fusion. On the other hand, in the second raw image mode, the image processing circuit performs image fusion on the raw Bayer image data, and demosaics and resamples the generated fused raw Bayer image. This may ensure a cleaner image signal for image fusion, but consumes more memory. The image processing circuit is configured to support both modes of operation, allowing for fused images to be generated to satisfy the requirements of different applications.

    Detecting keypoints in image data
    17.
    发明授权

    公开(公告)号:US11756163B2

    公开(公告)日:2023-09-12

    申请号:US17163245

    申请日:2021-01-29

    Applicant: Apple Inc.

    Inventor: David R. Pope

    Abstract: Methods and systems for detecting keypoints in image data may include an image sensor interface receiving pixel data from an image sensor. A front-end pixel data processing circuit may receive pixel data and convert the pixel data to a different color space format. A back-end pixel data processing circuit may perform one or more operations on the pixel data. An output circuit may receive pixel data and output the pixel data to a system memory. A keypoint detection circuit may receive pixel data from the image sensor interface in the image sensor pixel data format or receive pixel data after processing by the front-end or the back-end pixel data processing circuits. The keypoint detection circuit may perform a keypoint detection operation on the pixel data to detect one or more keypoints in the image frame and output to the system memory a description of the one or more keypoints.

    MULTI-MODE DEMOSAICING FOR RAW IMAGE DATA
    18.
    发明公开

    公开(公告)号:US20230232122A1

    公开(公告)日:2023-07-20

    申请号:US17578055

    申请日:2022-01-18

    Applicant: Apple Inc.

    CPC classification number: H04N9/04515 H04N9/67 H04N5/23229

    Abstract: Embodiments relate to a multi-mode demosaicing circuit able to receive and demosaic image data in a different raw image formats, such as Bayer raw image format and Quad Bayer raw image format. The multi-mode demosaicing circuit comprises different circuitry for demosaicing different image formats that access a shared working memory. In addition, the multi-mode demosaicing circuit shares memory with a post-processing and scaling circuit configured to perform subsequent post-processing and/or scaling of the demosaiced image data, in which the operations of the post-processing and scaling circuit are modified based on the original raw image format of the demosaiced image data to use different amounts of the shared memory, to compensate for additional memory utilized by the multi-mode demosaicing circuit when demosaicing certain types of image data.

    FRONT-END SCALER CIRCUIT FOR PROCESSING DEMOSAICED IMAGE DATA

    公开(公告)号:US20230230200A1

    公开(公告)日:2023-07-20

    申请号:US17578195

    申请日:2022-01-18

    Applicant: Apple Inc.

    CPC classification number: G06T3/4015 G06T5/002 G06T5/50 G06T2207/20212

    Abstract: Embodiments relate to a front-end scaler circuit configured to receive and process demosaiced image data in different modes depending on if the demosaiced image data was demosaiced from Bayer or Quad Bayer raw image data. The front-end scaler circuit shares memory with a demosaicing circuit, and is configured to perform different operations that use different amounts of the shared memory based on the original image format of the demosaiced image data being processed, to compensate for additional memory utilized by the demosaicing circuit when demosaicing certain types of image data. For example, when processing image data demosaiced from Quad Bayer image data, the front-end scaler circuit discards a portion of the chrominance component data for the received image data before performing chromatic suppression, compared to when processing image data demosaiced from Bayer image data.

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