公开(公告)号：US20130055191A1

公开(公告)日：2013-02-28

申请号：US13663755

申请日：2012-10-30

Applicant: Apple Inc.

Inventor： Antonietta Oliva ,  Gregory S. Scott ,  Edgardo F. Klass ,  Vincent R. von Kaenel

IPC: G06F17/50

CPC classification number: G06F17/5036

Abstract: A software tool and method for analyzing the reliability or failure rate of an integrated circuit (IC) are disclosed. The IC may include a plurality of circuit designs, and the software tool and method may aid a designer of the IC in determining a reliability rating of the IC based on reliability ratings of transistors or other circuit devices used in the circuit designs. In particular, the IC may include one or more circuit designs that have multiple instances within the IC (i.e., the same circuit design is instantiated multiple times), and the software tool and method may take into account the multiple instances when determining the reliability rating of the IC.

Abstract translation: 公开了一种用于分析集成电路（IC）的可靠性或故障率的软件工具和方法。 IC可以包括多个电路设计，并且该软件工具和方法可以帮助IC的设计者基于在电路设计中使用的晶体管或其它电路器件的可靠性等级来确定IC的可靠性等级。 特别地，IC可以包括在IC内具有多个实例的一个或多个电路设计（即，相同的电路设计被实例化多次），并且当确定可靠性等级时，软件工具和方法可以考虑多个实例 的IC。

公开(公告)号：US20180130524A1

公开(公告)日：2018-05-10

申请号：US15861308

申请日：2018-01-03

Applicant: Apple Inc.

Inventor： Brian J. Campbell ,  Vincent R. von Kaenel ,  Daniel C. Murray ,  Gregory S. Scott ,  Sribalan Santhanam

IPC: G11C11/419 ,  H03K19/0185

CPC classification number: G11C11/419 ,  G11C5/143 ,  G11C7/00 ,  G11C7/12 ,  G11C8/08 ,  G11C11/417 ,  H03K3/35613 ,  H03K19/018528

Abstract: In one embodiment, an integrated circuit includes at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method includes a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use.

公开(公告)号：US20140362639A1

公开(公告)日：2014-12-11

申请号：US14467633

申请日：2014-08-25

Applicant: Apple Inc.

Inventor： Brian J. Campbell ,  Vincent R. von Kaenel ,  Daniel C. Murray ,  Gregory S. Scott ,  Sribalan Santhanam

IPC: G11C11/419 ,  G11C7/12 ,  G11C8/08

CPC classification number: G11C11/419 ,  G11C5/143 ,  G11C7/00 ,  G11C7/12 ,  G11C8/08 ,  G11C11/417 ,  H03K3/35613 ,  H03K19/018528

Abstract: In one embodiment, an integrated circuit includes at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method includes a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use.

Abstract translation: 在一个实施例中，集成电路包括由第一电源电压提供的至少一个逻辑电路和耦合到逻辑电路并由第二电源电压提供的至少一个存储器电路。 即使在使用期间第一电源电压小于第二电源电压，存储器电路被配置为响应于逻辑电路被读取和写入。 在另一个实施例中，一种方法包括：读取存储单元的逻辑电路，由第一电源电压提供的逻辑电路; 并且所述存储单元响应于所读取的使用参考于所述第一电源电压的信号，其中所述存储单元被提供在使用期间大于所述第一电源电压的第二电源电压。

公开(公告)号：US20140092676A1

公开(公告)日：2014-04-03

申请号：US14095648

申请日：2013-12-03

Applicant: Apple Inc.

Inventor： Brian J. Campbell ,  Vincent R. von Kaenel ,  Daniel C. Murray ,  Gregory S. Scott ,  Sribalan Santhanam

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C5/143 ,  G11C7/00 ,  G11C7/12 ,  G11C8/08 ,  G11C11/417 ,  H03K3/35613 ,  H03K19/018528

Abstract: In one embodiment, an integrated circuit includes at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method includes a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use.