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公开(公告)号：US12034370B2
公开(公告)日：2024-07-09
申请号：US17651173
申请日：2022-02-15
Applicant: Apple Inc.
Inventor： Sujan K. Manohar , Jay B. Fletcher
Abstract: A power converter circuit included in a computer system magnetizes and de-magnetizes an inductor coupled to a switch node using high-side and low-side switches to alternatively couple a switch node to an input power supply node and a ground supply node. In response to detecting a drop in the voltage level of the input power supply node, the power converter circuit may adjust an on-resistance of the high-side switch to maintain performance at the lower voltage level of the input power supply node.
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公开(公告)号：US20230261573A1
公开(公告)日：2023-08-17
申请号：US17651173
申请日：2022-02-15
Applicant: Apple Inc.
Inventor： Sujan K. Manohar , Jay B. Fletcher
Abstract: A power converter circuit included in a computer system magnetizes and demagnetizes an inductor coupled to a switch node using high-side and low-side switches to alternatively couple a switch node to an input power supply node and a ground supply node. In response to detecting a drop in the voltage level of the input power supply node, the power converter circuit may adjust an on-resistance of the high-side switch to maintain performance at the lower voltage level of the input power supply node.
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公开(公告)号：US11303208B2
公开(公告)日：2022-04-12
申请号：US16290769
申请日：2019-03-01
Applicant: Apple Inc.
Inventor： Dingkun Du , Michael B. Nussbaum , Jitendra K. Agrawal , Floyd L. Dankert , Jay B. Fletcher
IPC: G06F1/28 , H02M3/158 , G06F1/3296
Abstract: A voltage regulator circuit included in a computer system may include multiple devices and a switch node coupled to a regulated power supply node via an inductor. The voltage regulator circuit may charge a capacitor using an input power supply signal, and couple the capacitor to the switch node using respective subsets of the multiple devices, which are selected based on one or more control signals. A control circuit may generate the one or more control signals based on a particular switching sequence, which is selected based on a ratio of a voltage level of the regulated power supply node and a voltage level input power supply signal.
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公开(公告)号：US20210089068A1
公开(公告)日：2021-03-25
申请号：US16583008
申请日：2019-09-25
Applicant: Apple Inc.
Inventor： Sujan K. Manohar , Jay B. Fletcher , Nathan F. Hanagami
Abstract: A dual loop LDO voltage regulator is disclosed. The voltage regulator circuit includes a first current mirror having first and second transistors having source terminals coupled to an input voltage node. The circuit further includes a second current mirror having third and fourth transistors, wherein drain terminals of the third and fourth transistors are coupled to drain terminals of the first and second transistors, respectively. A feedback circuit is coupled between source terminals of the third and fourth transistors, and is configured to generate a feedback signal based on a reference voltage and an output voltage present on the source terminal of the fourth transistor. The first and second current mirrors form a first control loop, and wherein the first and second current mirrors and the feedback circuit form a second control loop.
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公开(公告)号：US20150155780A1
公开(公告)日：2015-06-04
申请号：US14096868
申请日：2013-12-04
Applicant: Apple Inc.
Inventor： Shawn Searles , Jay B. Fletcher
IPC: H02M3/158
Abstract: A method and apparatus for monitoring instantaneous load current is disclosed. In one embodiment, an integrated circuit includes a voltage regulator and at least one functional unit implemented thereon. The voltage regulator includes a supply circuit configured to provide a voltage to the functional unit, and a sense circuit configured to determine an amount of current provided to the functional unit by the supply circuit. The sense circuit may determine the instantaneous load current being provided to the functional unit. An indication circuit is configured to provide, to the functional unit, an indication of the amount of current supplied thereto by the supply circuit.
Abstract translation: 公开了一种用于监测瞬时负载电流的方法和装置。 在一个实施例中，集成电路包括电压调节器和在其上实现的至少一个功能单元。 电压调节器包括被配置为向功能单元提供电压的供电电路，以及被配置为通过供电电路确定提供给功能单元的电流量的感测电路。 感测电路可以确定提供给功能单元的瞬时负载电流。 指示电路被配置为向功能单元提供由供应电路提供给其的电流量的指示。
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Patent Agency Ranking
公开(公告)号：US20250149984A1
公开(公告)日：2025-05-08
申请号：US19018305
申请日：2025-01-13
Applicant: Apple Inc.
Inventor： Victor Zyuban , Jay B. Fletcher , Hao Zhou
IPC: H02M3/158
Abstract: A power management circuit for computer systems includes a power converter circuit that generates different voltage levels at different time periods. Multiple voltage regulator circuits are coupled to the output of the power converter circuit and to respective local power supply nodes. Switch devices are used to bypass the voltage regulator circuits during corresponding ones of the different time periods.
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公开(公告)号：US12081124B2
公开(公告)日：2024-09-03
申请号：US17661509
申请日：2022-04-29
Applicant: Apple Inc.
Inventor： Jay B. Fletcher , Nathan F. Hanagami , Sanjay Pant , Hao Zhou , Shawn Searles
Abstract: A voltage regulator circuit included in a computer system may employ a control circuit and a switch array that includes multiple switch circuits. Different groups of switch circuits that include respective groups of switch devices are coupled between an input power supply node and corresponding regulated power supply nodes. To maintain desired respective voltages on the regulated power supply nodes, the control circuit compares the voltages of the regulated power supply nodes to corresponding reference voltages and, based on results of the comparisons, opens and closes various ones of the switch devices included in the different groups of switch circuits.
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公开(公告)号：US20240077932A1
公开(公告)日：2024-03-07
申请号：US18122410
申请日：2023-03-16
Applicant: Apple Inc.
Inventor： Talbott M. Houk , Wenxun Huang , Nikola Jovanovic , Floyd L. Dankert , Sanjay Pant , Alessandro Molari , Siarhei Meliukh , Nicola Florio , Ludmil N. Nikolov , Nathan F. Hanagami , Hartmut Sturm , Di Zhao , Chad L. Olson , John J. Sullivan , Seyedeh Maryam Mortazavi Zanjani , Tristan R. Hudson , Jay B. Fletcher , Jonathan A. Dutra
IPC: G06F1/3296 , G06F1/3212 , G06F1/3234
CPC classification number: G06F1/3296 , G06F1/3212 , G06F1/3278
Abstract: The present disclosure describes a system with a power management device, a wakeup circuit, a battery management device, and a connector. During a powered down mode of operation, the battery management device can provide, via the connector, a bias voltage to the wakeup circuit. In response to a wakeup switch being activated, the battery management device can provide a power supply (e.g., from a battery) to the power management device. Benefits of the wakeup circuit include (1) a reduction of battery consumption—and thus improving battery lifetime—when the electronic system is in a powered down mode of operation because the wakeup circuit has lower number of active components compared to other designs and (2) a non-complex wakeup circuit design because one or more existing connector interconnects between the power management device and the battery management device can be re-used during electronic system's powered down mode of operation.
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公开(公告)号：US11695336B2
公开(公告)日：2023-07-04
申请号：US17343459
申请日：2021-06-09
Applicant: Apple Inc.
Inventor： Hao Zhou , Sarfraz Shaikh , Jay B. Fletcher , Sanjay Pant , Mark A. Yoshimoto , Vincenzo Bisogno , Shawn Searles
Abstract: A power management circuit included in a computer system regulates a voltage level of a power supply node used by other circuits in the computer system. The power management circuit includes a control circuit and multiple phase circuits coupled to the regulated power supply node via corresponding inductors. The control circuit selectively activates particular ones of the multiple phase circuits allowing them source respective currents to the regulated power supply node. The control circuit also selectively activates particular ones of other phase circuits that are external to the power management circuit and coupled to the regulated power supply node via their own corresponding inductors. Once activated, the external phase circuits source respective currents to the regulated power supply node via their corresponding inductors.
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公开(公告)号：US20230048248A1
公开(公告)日：2023-02-16
申请号：US17823027
申请日：2022-08-29
Applicant: Apple Inc.
Inventor： Jay B. Fletcher
IPC: H02M3/158
Abstract: A voltage regulator having a multi-level, multi-phase architecture is disclosed. The circuit includes a two-level buck converter and an N-level buck converter each coupled to an output node, wherein N is an integer value of three or more. During operation, the two-level buck converter provides one of two possible voltages to a first inductor. The N-level buck converter provides, during operation, one of N voltages to a second inductor. The first and second inductors each convert respectively received voltages to currents, which are provided to a common output node. A control circuit controls the activation of transistors in each of the two-level and N-level buck converters in such a manner as to cause the voltage on the output node to be maintained at a desired level.
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