Efficient retention flop utilizing different voltage domain

    公开(公告)号:US11418174B2

    公开(公告)日:2022-08-16

    申请号:US17245623

    申请日:2021-04-30

    申请人: Apple Inc.

    IPC分类号: H03K3/037 G11C19/18 H03K3/356

    摘要: A system and method for efficiently retaining data in sequential elements during power down modes. In various embodiments, a master latch of a flip-flop circuit receives an always-on first power supply voltage, whereas, a slave latch and other surrounding circuitry receives a second power supply voltage capable of being powered down. During a power down mode, circuitry consumes less power while the master latch retains stored data. In some designs, the flip-flop circuit is a level shifting circuit, and the always-on first power supply voltage is less than the second power supply voltage. The master latch uses complex gates with a p-type transistor at the top of a stack of p-type transistors receiving the always-on power supply voltage level on its source terminal and the retained data value on its gate terminal. This top p-type transistor is capable of remaining disabled even when used in a level shifting manner.

    Voltage Regulation Using Local Feedback

    公开(公告)号:US20220066490A1

    公开(公告)日:2022-03-03

    申请号:US17006707

    申请日:2020-08-28

    申请人: Apple Inc.

    IPC分类号: G05F1/575 H03K17/22

    摘要: A voltage regulator circuit may generate a regulated voltage level using a voltage level of a feedback node. The regulated voltage level may be distributed, via a power distribution network, to package power supply node of a package, into which an integrated circuit has been mounted. Power switches included in the integrated circuit may couple the package power supply node to respective local power supply nodes in the integrated circuit. A particular power switch may selectively couple different ones of the local power supply nodes to the feedback node, allowing the voltage regulator circuit to compensate for reductions in the regulated voltage level due to the power distribution network, as well as adjust the regulated voltage level based on power consumptions of load circuits coupled to the local power supply nodes.

    Generating an overdrive voltage for power switch circuitry

    公开(公告)号:US09871507B1

    公开(公告)日:2018-01-16

    申请号:US15264365

    申请日:2016-09-13

    申请人: Apple Inc.

    IPC分类号: G05F3/02 H03K17/16 H03K5/24

    摘要: Techniques are disclosed relating to generating an overdrive voltage for power switch circuitry. In some embodiments, the value of the overdrive voltage is adjusted dynamically in order to reduce leakage current during power gating. In some embodiments, an apparatus includes a power switch circuit element configured to gate power to circuitry in the apparatus based on a control signal. In some embodiments, the power switch circuit element is powered by a supply voltage. In some embodiments, the apparatus also includes control circuitry configured to generate the control voltage at a different voltage level than the supply voltage, based on comparison of leakage current of ones of a plurality of replicas of the power switch circuit element. In some embodiments, the replicas are configured to receive different reference voltages as respective replica control signals. In various embodiments, the disclosed techniques may generate overdrive voltages that reduce leakage current during power gating.

    FLIP FLOP USING DUAL INVERTER FEEDBACK

    公开(公告)号:US20170264274A1

    公开(公告)日:2017-09-14

    申请号:US15066809

    申请日:2016-03-10

    申请人: Apple Inc.

    IPC分类号: H03K3/3562

    CPC分类号: H03K3/35625 H03K3/356173

    摘要: Embodiments of the present disclosure relate to a flip flop circuit that obviates the need of a transmission gate. The flip flop includes a first match multiplexer, a second match multiplexer and a separable inverter. The first match multiplexer receives an input data signal and generates a feedback output based on the input data signal and the logic levels at two nodes coupled to the first match multiplexer. The separable inverter receives the feedback output and switches the logic level of one of two nodes but maintains the logic level per each clock cycle. The second match multiplexer generates a signal output based on the logic levels at the two nodes and the signal output that is fed back into the second match multiplexer. Embodiments may reduce power consumption and operate at lower voltages.

    Voltage regulation using local feedback

    公开(公告)号:US11675380B2

    公开(公告)日:2023-06-13

    申请号:US17658408

    申请日:2022-04-07

    申请人: Apple Inc.

    IPC分类号: G05F1/575 H03K17/22

    CPC分类号: G05F1/575 H03K17/223

    摘要: A voltage regulator circuit may generate a regulated voltage level using a voltage level of a feedback node. The regulated voltage level may be distributed, via a power distribution network, to package power supply node of a package, into which an integrated circuit has been mounted. Power switches included in the integrated circuit may couple the package power supply node to respective local power supply nodes in the integrated circuit. A particular power switch may selectively couple different ones of the local power supply nodes to the feedback node, allowing the voltage regulator circuit to compensate for reductions in the regulated voltage level due to the power distribution network, as well as adjust the regulated voltage level based on power consumptions of load circuits coupled to the local power supply nodes.

    Power switch multiplexer with configurable overlap

    公开(公告)号:US10908663B2

    公开(公告)日:2021-02-02

    申请号:US16433801

    申请日:2019-06-06

    申请人: Apple Inc.

    摘要: A power switch multiplexer with configurable overlap is disclosed. An integrated circuit (IC) includes a first functional circuit block coupled to receive a supply voltage from a first supply voltage node. The IC further includes an input circuit and an output circuit. Responsive to receiving an input signal, the input circuit asserts an activation signal to cause one of a second supply voltage node and a third supply voltage node to be electrically coupled to the first supply voltage node. Subsequently the input circuit asserts a deactivation signal to cause the other one of the second and third supply voltage nodes to be electrically decoupled from the first supply voltage node. The output circuit is coupled to receive the activation signal and the deactivation signal, and configured to assert a first output signal subsequent to receiving the activation signal.

    Method for multiplexing between power supply signals for voltage limited circuits

    公开(公告)号:US10763859B2

    公开(公告)日:2020-09-01

    申请号:US16687026

    申请日:2019-11-18

    申请人: Apple Inc.

    摘要: In an embodiment, a system includes a plurality of functional circuits, a power supply circuit, and a power management circuit. The power supply circuit may generate a shared power signal coupled to each of the functional circuits, and to generate a plurality of adjustable power signals. One adjustable power signal may be coupled to a particular functional circuit of the functional circuits. The power management circuit may a request to the power supply circuit to change a voltage level of the one particular adjustable power signal from a first voltage to a second voltage. The particular functional circuit may couple a respective power node for a sub-circuit of the particular functional circuit to either of the shared power signal or the particular adjustable power signal. The particular functional circuit may also be configured to maintain an operational voltage level on the power node.

    METHOD FOR MULTIPLEXING BETWEEN POWER SUPPLY SIGNALS FOR VOLTAGE LIMITED CIRCUITS

    公开(公告)号:US20200162077A1

    公开(公告)日:2020-05-21

    申请号:US16687026

    申请日:2019-11-18

    申请人: Apple Inc.

    IPC分类号: H03K19/0175 G11C5/14 H03K5/01

    摘要: In an embodiment, a system includes a plurality of functional circuits, a power supply circuit, and a power management circuit. The power supply circuit may generate a shared power signal coupled to each of the functional circuits, and to generate a plurality of adjustable power signals. One adjustable power signal may be coupled to a particular functional circuit of the functional circuits. The power management circuit may a request to the power supply circuit to change a voltage level of the one particular adjustable power signal from a first voltage to a second voltage. The particular functional circuit may couple a respective power node for a sub-circuit of the particular functional circuit to either of the shared power signal or the particular adjustable power signal. The particular functional circuit may also be configured to maintain an operational voltage level on the power node.

    Low leakage power switch
    9.
    发明授权

    公开(公告)号:US10523194B2

    公开(公告)日:2019-12-31

    申请号:US15717276

    申请日:2017-09-27

    申请人: Apple Inc.

    摘要: A power switch control circuit is disclosed. A sensor circuit may determine a leakage current of a power switch coupled to a power supply signal and a power terminal of a circuit block. The power switch may be configured to selectively couple or decouple the circuit block from the power supply signal using a switch control signal. The switch control circuit may, in response to receiving a request to open the power switch, determine a target voltage level that is greater than a voltage level of the power supply signal for the switch control signal using the leakage current, and transition the switch control signal from an initial voltage to the target voltage level.

    Flip flop using dual inverter feedback

    公开(公告)号:US09929723B2

    公开(公告)日:2018-03-27

    申请号:US15066809

    申请日:2016-03-10

    申请人: Apple Inc.

    IPC分类号: H03K3/3562 H03K3/356

    CPC分类号: H03K3/35625 H03K3/356173

    摘要: Embodiments of the present disclosure relate to a flip flop circuit that obviates the need of a transmission gate. The flip flop includes a first match multiplexer, a second match multiplexer and a separable inverter. The first match multiplexer receives an input data signal and generates a feedback output based on the input data signal and the logic levels at two nodes coupled to the first match multiplexer. The separable inverter receives the feedback output and switches the logic level of one of two nodes but maintains the logic level per each clock cycle. The second match multiplexer generates a signal output based on the logic levels at the two nodes and the signal output that is fed back into the second match multiplexer. Embodiments may reduce power consumption and operate at lower voltages.