公开(公告)号：US11650825B2

公开(公告)日：2023-05-16

申请号：US17668869

申请日：2022-02-10

Applicant: Apple Inc.

Inventor： Aditya Kesiraju ,  Rajdeep L. Bhuyar ,  Ran A. Chachick ,  Andrew J. Beaumont-Smith

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3877 ,  G06F9/30087 ,  G06F9/3838

Abstract: An instruction set architecture including instructions for a processor and instructions for a coprocessor may include synchronizing instructions that may be used to begin and end instruction sequences that include coprocessor instructions (coprocessor sequences). If a terminating synchronizing instruction is followed by an initial synchronizing instruction and the pair are detected in the coprocessor concurrently, the coprocessor may suppress execution of the pair of instructions.

公开(公告)号：US20220350776A1

公开(公告)日：2022-11-03

申请号：US17869617

申请日：2022-07-20

Applicant: Apple Inc.

Inventor： Aditya Kesiraju ,  Andrew J. Beaumont-Smith ,  Boris S. Alvarez-Heredia ,  Ran A. Chachick

IPC: G06F15/80 ,  G06F7/544 ,  G06F7/57 ,  G06F9/38

Abstract: In an embodiment, a coprocessor may include a bypass indication which identifies execution circuitry that is not used by a given processor instruction, and thus may be bypassed. The corresponding circuitry may be disabled during execution, preventing evaluation when the output of the circuitry will not be used for the instruction. In another embodiment, the coprocessor may implement a grid of processing elements in rows and columns, where a given coprocessor instruction may specify an operation that causes up to all of the processing elements to operate on vectors of input operands to produce results. Implementations of the coprocessor may implement a portion of the processing elements. The coprocessor control circuitry may be designed to operate with the full grid or partial grid, reissuing instructions in the partial grid case to perform the requested operation. In still another embodiment, the coprocessor may be able to fuse vector mode operations.

公开(公告)号：US20200272467A1

公开(公告)日：2020-08-27

申请号：US16286213

申请日：2019-02-26

Applicant: Apple Inc.

Inventor： Aditya Kesiraju ,  Andrew J. Beaumont-Smith ,  Deepankar Duggal ,  Ran A. Chachick

IPC: G06F9/345 ,  G06F9/38 ,  G06F9/30

Abstract: In an embodiment, a coprocessor includes multiple processing elements arranged in a grid of one or more rows and one or more columns. A given processing element includes an arithmetic/logic unit (ALU) circuit configured to perform an ALU operation specified by an instruction executable by the coprocessor, wherein the ALU circuit is configured to produce a result. The given processing element further comprises a first memory coupled to the execute circuit. The first memory is configured to store results generated by the given processing element. The first memory includes a portion of a result memory implemented by the coprocessor, wherein locations in the result memory are specifiable as destination operands of instructions executable by the coprocessor. The portion of the result memory implemented by the first memory is the portion of the result memory that the given processing element is capable of updating.