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1.发明申请公开(公告)号：US20220358082A1
公开(公告)日：2022-11-10
申请号：US17869620
申请日：2022-07-20
Applicant: Apple Inc.
Inventor： Aditya Kesiraju , Andrew J. Beaumont-Smith , Boris S. Alvarez-Heredia , Pradeep Kanapathipillai , Ran A. Chachick
Abstract: In an embodiment, a coprocessor may include a bypass indication which identifies execution circuitry that is not used by a given processor instruction, and thus may be bypassed. The corresponding circuitry may be disabled during execution, preventing evaluation when the output of the circuitry will not be used for the instruction. In another embodiment, the coprocessor may implement a grid of processing elements in rows and columns, where a given coprocessor instruction may specify an operation that causes up to all of the processing elements to operate on vectors of input operands to produce results. Implementations of the coprocessor may implement a portion of the processing elements. The coprocessor control circuitry may be designed to operate with the full grid or partial grid, reissuing instructions in the partial grid case to perform the requested operation. In still another embodiment, the coprocessor may be able to fuse vector mode operations.
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2.发明授权公开(公告)号：US12174785B2
公开(公告)日：2024-12-24
申请号：US17869620
申请日：2022-07-20
Applicant: Apple Inc.
Inventor： Aditya Kesiraju , Andrew J. Beaumont-Smith , Boris S. Alvarez-Heredia , Pradeep Kanapathipillai , Ran A. Chachick
Abstract: In an embodiment, a coprocessor may include a bypass indication which identifies execution circuitry that is not used by a given processor instruction, and thus may be bypassed. The corresponding circuitry may be disabled during execution, preventing evaluation when the output of the circuitry will not be used for the instruction. In another embodiment, the coprocessor may implement a grid of processing elements in rows and columns, where a given coprocessor instruction may specify an operation that causes up to all of the processing elements to operate on vectors of input operands to produce results. Implementations of the coprocessor may implement a portion of the processing elements. The coprocessor control circuitry may be designed to operate with the full grid or partial grid, reissuing instructions in the partial grid case to perform the requested operation. In still another embodiment, the coprocessor may be able to fuse vector mode operations.
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3.发明授权公开(公告)号：US11429555B2
公开(公告)日：2022-08-30
申请号：US16286170
申请日：2019-02-26
Applicant: Apple Inc.
Inventor： Aditya Kesiraju , Andrew J. Beaumont-Smith , Boris S. Alvarez-Heredia , Srikanth Balasubramanian
Abstract: In an embodiment, a coprocessor may include a bypass indication which identifies execution circuitry that is not used by a given processor instruction, and thus may be bypassed. The corresponding circuitry may be disabled during execution, preventing evaluation when the output of the circuitry will not be used for the instruction. In another embodiment, the coprocessor may implement a grid of processing elements in rows and columns, where a given coprocessor instruction may specify an operation that causes up to all of the processing elements to operate on vectors of input operands to produce results. Implementations of the coprocessor may implement a portion of the processing elements. The coprocessor control circuitry may be designed to operate with the full grid or partial grid, reissuing instructions in the partial grid case to perform the requested operation. In still another embodiment, the coprocessor may be able to fuse vector mode operations.
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4.发明授权公开(公告)号：US12135681B2
公开(公告)日：2024-11-05
申请号：US17869617
申请日：2022-07-20
Applicant: Apple Inc.
Abstract: In an embodiment, a coprocessor may include a bypass indication which identifies execution circuitry that is not used by a given processor instruction, and thus may be bypassed. The corresponding circuitry may be disabled during execution, preventing evaluation when the output of the circuitry will not be used for the instruction. In another embodiment, the coprocessor may implement a grid of processing elements in rows and columns, where a given coprocessor instruction may specify an operation that causes up to all of the processing elements to operate on vectors of input operands to produce results. Implementations of the coprocessor may implement a portion of the processing elements. The coprocessor control circuitry may be designed to operate with the full grid or partial grid, reissuing instructions in the partial grid case to perform the requested operation. In still another embodiment, the coprocessor may be able to fuse vector mode operations.
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Patent Agency Ranking
5.发明申请公开(公告)号：US20220350776A1
公开(公告)日：2022-11-03
申请号：US17869617
申请日：2022-07-20
Applicant: Apple Inc.
Abstract: In an embodiment, a coprocessor may include a bypass indication which identifies execution circuitry that is not used by a given processor instruction, and thus may be bypassed. The corresponding circuitry may be disabled during execution, preventing evaluation when the output of the circuitry will not be used for the instruction. In another embodiment, the coprocessor may implement a grid of processing elements in rows and columns, where a given coprocessor instruction may specify an operation that causes up to all of the processing elements to operate on vectors of input operands to produce results. Implementations of the coprocessor may implement a portion of the processing elements. The coprocessor control circuitry may be designed to operate with the full grid or partial grid, reissuing instructions in the partial grid case to perform the requested operation. In still another embodiment, the coprocessor may be able to fuse vector mode operations.
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6.发明申请公开(公告)号：US20250094381A1
公开(公告)日：2025-03-20
申请号：US18959080
申请日：2024-11-25
Applicant: Apple Inc.
Inventor： Aditya Kesiraju , Andrew J. Beaumont-Smith , Boris S. Alvarez-Heredia , Pradeep Kanapathipillai , Ran A. Chachick
Abstract: In an embodiment, a coprocessor may include a plurality of processing element circuits arranged in a first grid, where a given coprocessor instruction of an instruction set for the coprocessor is defined to cause evaluation of a second plurality of processing element circuits arranged in a second grid, where the second grid includes more processing element circuits than the first grid. The coprocessor may further include a scheduler circuit configured to issue instruction operations to the plurality of processing element circuits, where the scheduler circuit is configured to issue a given instruction operation corresponding to the given coprocessor instruction a plurality of times to complete the given coprocessor instruction, wherein different issuances of the given instruction operation are configured to cause respective different portions of the evaluation defined by the given coprocessor instruction to be performed.
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公开(公告)号：US10969858B2
公开(公告)日：2021-04-06
申请号：US16238984
申请日：2019-01-03
Applicant: Apple Inc.
Inventor： Daniel U. Becker , Aditya Kesiraju , Srikanth Balasubramanian , Venkatram Krishnaswamy , Boris S. Alvarez-Heredia
Abstract: In an embodiment, a power control circuit for an execute circuit is configured to monitor power consumption of operations in a pipeline of the execute circuit and potential changes in power consumption if new operations are issued into the pipeline. The power control circuit may be configured to inhibit issuance of a given operation if the change in power consumption is greater than a maximum increase. A decaying average of previous power consumptions may be maintained and compared to the potential increase in power consumption to control the rate of change in power consumption over time.
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8.发明申请公开(公告)号：US20200272597A1
公开(公告)日：2020-08-27
申请号：US16286170
申请日：2019-02-26
Applicant: Apple Inc.
Inventor： Aditya Kesiraju , Andrew J. Beaumont-Smith , Boris S. Alvarez-Heredia , Pradeep Kanapathipillai , Ran A. Chachick , Srikanth Balasubramanian
Abstract: In an embodiment, a coprocessor may include a bypass indication which identifies execution circuitry that is not used by a given processor instruction, and thus may be bypassed. The corresponding circuitry may be disabled during execution, preventing evaluation when the output of the circuitry will not be used for the instruction. In another embodiment, the coprocessor may implement a grid of processing elements in rows and columns, where a given coprocessor instruction may specify an operation that causes up to all of the processing elements to operate on vectors of input operands to produce results. Implementations of the coprocessor may implement a portion of the processing elements. The coprocessor control circuitry may be designed to operate with the full grid or partial grid, reissuing instructions in the partial grid case to perform the requested operation. In still another embodiment, the coprocessor may be able to fuse vector mode operations.
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公开(公告)号：US20200218327A1
公开(公告)日：2020-07-09
申请号：US16238984
申请日：2019-01-03
Applicant: Apple Inc.
Inventor： Daniel U. Becker , Aditya Kesiraju , Srikanth Balasubramanian , Venkatram Krishnaswamy , Boris S. Alvarez-Heredia
IPC: G06F1/329
Abstract: In an embodiment, a power control circuit for an execute circuit is configured to monitor power consumption of operations in a pipeline of the execute circuit and potential changes in power consumption if new operations are issued into the pipeline. The power control circuit may be configured to inhibit issuance of a given operation if the change in power consumption is greater than a maximum increase. A decaying average of previous power consumptions may be maintained and compared to the potential increase in power consumption to control the rate of change in power consumption over time.
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