公开(公告)号：US20240250709A1

公开(公告)日：2024-07-25

申请号：US18157772

申请日：2023-01-20

Applicant: Apple Inc.

Inventor： Omar A Abdelatty ,  Kefei Wu ,  Woorim Shin ,  Yi Zhao

IPC: H04B1/40

CPC classification number: H04B1/40

Abstract: An electronic device may be provided with wireless circuitry that includes a transceiver. The transceiver may include a first signal path and a second signal path extending parallel to the first signal path. The first signal path may include a first chain of gain stages and a first inductive matching network. The second signal path may include a second chain of gain stages and a second inductive matching network. The first inductive matching network may be magnetically coupled to the second inductive matching network. The first and/or second signal path may include one or more crossovers that invert a polarity of the signals on the signal paths. The crossovers may help to mitigate the effects of the magnetic coupling between the first and second signal paths while allowing for minimal spatial separation between the signal paths.

公开(公告)号：US20230336186A1

公开(公告)日：2023-10-19

申请号：US18338920

申请日：2023-06-21

Applicant: Apple Inc.

Inventor： Yi Zhao ,  David M. Signoff

IPC: H03M1/74 ,  H04B1/40

CPC classification number: H03M1/74 ,  H04B1/40 ,  H03K19/20

Abstract: A number of unit cells of a digital-to-analog converter (DAC) may be simultaneously activated to generate an analog signal. However, while each unit cell may be generally the same, there may be variations such as non-linearity or noise in the analog output depending on which unit cells are activated for a given digital signal value. For example, as additional unit cells are activated for increased values of the analog signal, the fill order in which the unit cells are activated may affect the linearity/noise of the DAC. The decision units may be programmable to select which branches of the fractal DAC to activate, changing the fill order based on a fill-selection signal. The fill order may be set by a fill controller via the fill-selection signal to account for manufacturing variations, gradients in the supply voltage, output line routing, and/or environmental factors such as temperature.

公开(公告)号：US11700011B2

公开(公告)日：2023-07-11

申请号：US17471786

申请日：2021-09-10

Applicant: Apple Inc.

Inventor： Yi Zhao ,  David M. Signoff

IPC: H03M1/74 ,  H04B1/40 ,  H03K19/20

CPC classification number: H03M1/74 ,  H04B1/40 ,  H03K19/20

Abstract: A number of unit cells of a digital-to-analog converter (DAC) may be simultaneously activated to generate an analog signal. However, while each unit cell may be generally the same, there may be variations such as non-linearity or noise in the analog output depending on which unit cells are activated for a given digital signal value. For example, as additional unit cells are activated for increased values of the analog signal, the fill order in which the unit cells are activated may affect the linearity/noise of the DAC. The decision units may be programmable to select which branches of the fractal DAC to activate, changing the fill order based on a fill-selection signal. The fill order may be set by a fill controller via the fill-selection signal to account for manufacturing variations, gradients in the supply voltage, output line routing, and/or environmental factors such as temperature.

公开(公告)号：US09488692B2

公开(公告)日：2016-11-08

申请号：US14468394

申请日：2014-08-26

Applicant: Apple Inc.

Inventor： Asad A. Bawa ,  Benjamin A. Marrou ,  Christopher Ng ,  Michael R. Seningen ,  Mihir S. Sabnis ,  Zameeruddin Mohammed ,  Yi Zhao

IPC: G01R31/3185 ,  G01R31/3177

CPC classification number: G01R31/318552 ,  G01R31/3177 ,  G01R31/318541 ,  G01R31/318563 ,  G01R31/318575

Abstract: A method and apparatus for implementing mode based skew is disclosed. In one embodiment, an IC includes a number of different functional units each coupled to receive a respective one of a number of different clock signals. One or more of the functional circuit blocks includes at least two clock-gating circuits that are coupled to receive the clock signal provided to that functional circuit block. During a scan test, a first clock-gating circuit within a functional circuit block is configured to provide a first delay to the clock signal. A second clock-gating circuit within the functional circuit block may provide a second delay to the clock signal, the second delay being different from the first.

Abstract translation: 公开了一种用于实现基于模式的偏斜的方法和装置。 在一个实施例中，IC包括多个不同的功能单元，每个功能单元被耦合以接收多个不同时钟信号中的相应一个。 一个或多个功能电路块包括至少两个时钟门控电路，其被耦合以接收提供给该功能电路块的时钟信号。 在扫描测试期间，功能电路块内的第一时钟选通电路被配置为向时钟信号提供第一延迟。 功能电路块内的第二时钟选通电路可以向时钟信号提供第二延迟，第二延迟与第一延迟不同。