Abstract:
A display may have an array of pixels. Due to the presence of a notch in the display, the display may have some rows that are shorter than other rows in the display, and accordingly different gate line loading. To account for the gate line loading variations, the display driver circuitry may have gate driver circuits that provide different gate line signals to different rows of pixels within the display. In other arrangement, luminance adjustment circuitry may receive image data and generate corresponding compensated image data to account for gate line loading variations between rows of pixels in the display. The image data may be compensated based on the location of the pixel, the gray level of the image data, the display brightness, and/or temperature.
Abstract:
An organic light-emitting diode display may contain an array of display pixels. Each display pixel may have a respective organic light-emitting diode that is controlled by a drive transistor. At low temperatures, it may be necessary to increase the amount of current through an organic light-emitting diode to achieve a desired luminance level. In order to increase the current through the light-emitting diode, the ground voltage level may be lowered. However, this may lead to thin-film transistors within the pixel leaking, which may result in undesirable display artifacts such as bright dots being displayed in a dark image. In order to prevent leakage in the transistors, the transistors may be coupled to separate reference voltage supplies or separate control lines. Additionally, the transistors may be positioned to minimize leakage even at low ground voltage levels.
Abstract:
A display device may include rows of pixels that may display image data on a display and a circuit. The circuit may perform a progressive scan across the rows of pixels to display the image data using a plurality of pixels, supply test data to a pixel of plurality of pixels that corresponds to a first row of the rows of pixels during one frame of the progressive scan, and initiate a sensing period for determining one or more sensitivity properties associated with the pixel based on the performance of the pixel with respect to the test data in response to receiving a pulse of a first global signal. The circuit may then end the sensing period in response to receiving a second global signal and resume the progressive scan across the rows of pixels to display the image data after the sensing period ends.
Abstract:
A display having thin-film transistor (TFT) structures may be used to display images within an active area of the display, which is surrounded by an inactive border area. In order to reduce the inactive area, a TFT passivation layer may be used to help protect conductive routing lines at the outer edge of the border so that encapsulation layers need not be formed all the way to the edge. At least some of the conductive routing lines in the inactive area may be stacked or coupled in parallel to help reduce border width. The TFT passivation layer may also cover the lateral edges of the routing lines to help prevent corrosion during an anode etch. The encapsulation layers may also be formed in a bent portion of the display substrate to help adjust the neutral stress plane such that metal traces formed in the bent portion do not crack.
Abstract:
A display having thin-film transistor (TFT) structures may be used to display images within an active area of the display, which is surrounded by an inactive border area. In order to reduce the inactive area, a TFT passivation layer may be used to help protect conductive routing lines at the outer edge of the border so that encapsulation layers need not be formed all the way to the edge. At least some of the conductive routing lines in the inactive area may be stacked or coupled in parallel to help reduce border width. The TFT passivation layer may also cover the lateral edges of the routing lines to help prevent corrosion during an anode etch. The encapsulation layers may also be formed in a bent portion of the display substrate to help adjust the neutral stress plane such that metal traces formed in the bent portion do not crack.
Abstract:
An electronic device display may have an array of pixel circuits. Each pixel circuit may include an organic light-emitting diode and a drive transistor. Each drive transistor may be adjusted to control how much current flows through the organic light-emitting diode. Each pixel circuit may include one or more additional transistors such as switching transistors and a storage capacitor. Semiconducting oxide transistors and silicon transistors may be used in forming the transistors of the pixel circuits. The storage capacitors and the transistors may be formed using metal layers, semiconductor structures, and dielectric layers. Some of the layers may be removed along the edge of the display to facilitate bending. The dielectric layers may have a stepped profile that allows data lines in the array to be stepped down towards the surface of the substrate as the data lines extend into an inactive edge region.
Abstract:
An organic light-emitting diode display may have an array of pixels. Each pixel may have an organic light-emitting diode with an anode and cathode. The anodes may be formed from a patterned layer of metal. Thin-film transistor circuitry in the pixels may include transistors such as drive transistors and switching transistors. Data lines may supply data signals to the pixels and horizontal control lines may supply control signals to the gates of the transistors. A switching transistor may be coupled between a voltage initialization line and each anode. The voltage initialization lines and capacitor structures in the thin-film transistor circuitry may be formed using a layer of metal that is different than the layer of metal that forms the anodes.
Abstract:
This application sets forth a circuit configuration for a light emitting diode (LED) or organic light emitting diode (OLED) display. The circuit configuration allows for the pulse-width modulation (PWM) of each emission signal sent to each line of the display. The PWM of each emission signal is accomplished using a gate-in-panel (GIP) controller of the display. The GIP controller uses an arrangement of shift register outputs and a programmable clock input to control an output of an inverter that provides the emission signal. The programmable clock input can be programmed according to a desired timing or duty cycle for the emission signal. In this way, by limiting the duty cycle of the emission signal, dimming and other display features can be exhibited by the LED or OLED display.
Abstract:
A display may have an array of organic light-emitting diode display pixels. Each display pixel may have a light-emitting diode that emits light under control of a drive transistor. Each display pixel may also have control transistors for compensating and programming operations. The array of display pixels may have rows and columns. Row lines may be used to apply row control signals to rows of the display pixels. Column lines (data lines) may be used to apply display data and other signals to respective columns of display pixels. A bottom conductive shielding structure may be formed below each drive transistor. The bottom conductive shielding structure may serve to shield the drive transistor from any electric field generated from the adjacent row and column lines. The bottom conductive shielding structure may be electrically floating or coupled to a power supply line.
Abstract:
An organic light-emitting diode display may have thin-film transistor circuitry formed on a substrate. The display and substrate may have rounded corners. A pixel definition layer may be formed on the thin-film transistor circuitry. Openings in the pixel definition layer may be provided with emissive material overlapping respective anodes for organic light-emitting diodes. A cathode layer may cover the array of pixels. A ground power supply path may be used to distribute a ground voltage to the cathode layer. The ground power supply path may be formed from a metal layer that is shorted to the cathode layer using portions of a metal layer that forms anodes for the diodes, may be formed from a mesh shaped metal pattern, may have L-shaped path segments, may include laser-deposited metal on the cathode layer, and may have other structures that facilitate distribution of the ground power supply.