公开(公告)号：US10725992B2

公开(公告)日：2020-07-28

申请号：US16207241

申请日：2018-12-03

Applicant: ARM LIMITED

Inventor： Mitchell Bryan Hayenga ,  Curtis Glenn Dunham ,  Dam Sunwoo

IPC: G06F16/22 ,  G06F12/0875 ,  G06F12/1009 ,  G06F12/1027 ,  G06F9/38 ,  G06F16/172 ,  G06F21/75

Abstract: An apparatus has processing circuitry for processing instructions from multiple threads. A storage structure is shared between the threads and has a number of entries. Indexing circuitry generates a target index value identifying an entry of the storage structure to be accessed in response to a request from the processing circuitry specifying a requested index value corresponding to information to be accessed from the storage structure. The indexing circuitry generates the target index value as a function of the requested index value and a key value selected depending on which of the threads trigger the request. The key value for at least one of the threads is updated from time to time.

公开(公告)号：US11899583B2

公开(公告)日：2024-02-13

申请号：US17388927

申请日：2021-07-29

Applicant: Arm Limited

Inventor： Joshua Randall ,  Alejandro Rico Carro ,  Dam Sunwoo ,  Saurabh Pijuskumar Sinha ,  Jamshed Jalal

IPC: G06F12/0811 ,  G06F12/084 ,  H04L45/42 ,  H04L49/109 ,  G06F12/0813 ,  G06F12/0893

CPC classification number: G06F12/0811 ,  G06F12/084 ,  G06F12/0813 ,  G06F12/0893 ,  H04L45/42 ,  H04L49/109

Abstract: Various implementations described herein are directed to a device with a multi-layered logic structure with multiple layers including a first layer and a second layer arranged vertically in a stacked configuration. The device may have a first cache memory with first interconnect logic disposed in the first layer. The device may have a second cache memory with second interconnect logic disposed in the second layer, wherein the second interconnect logic in the second layer is linked to the first interconnect logic in the first layer.

公开(公告)号：US20210026826A1

公开(公告)日：2021-01-28

申请号：US16519498

申请日：2019-07-23

Applicant: Arm Limited

Inventor： Kim Gwangsun ,  Dam Sunwoo

IPC: G06F16/22

Abstract: Briefly, example methods, apparatuses, devices, and/or articles of manufacture are disclosed that may be implemented, in whole or in part, using one or more processing devices to facilitate and/or support one or more operations and/or techniques to access entries in a hash table. In a particular implementation, a hash operation may be selected from between or among multiple hash operations to map key values to entries in a hash table.

公开(公告)号：US10817426B2

公开(公告)日：2020-10-27

申请号：US16139160

申请日：2018-09-24

Applicant: Arm Limited

Inventor： Krishnendra Nathella ,  Chris Abernathy ,  Huzefa Moiz Sanjeliwala ,  Dam Sunwoo ,  Balaji Vijayan

IPC: G06F12/0862 ,  G06F9/30

Abstract: A variety of data processing apparatuses are provided in which stride determination circuitry determines a stride value as a difference between a current address and a previously received address. Stride storage circuitry stores an association between stride values determined by the stride determination circuitry and a frequency during a training period. Prefetch circuitry causes a further data value to be proactively retrieved from a further address. The further address is the current address modified by a stride value in the stride storage circuitry having a highest frequency during the training period. The variety of data processing apparatuses are directed towards improving efficiency by variously disregarding certain candidate stride values, considering additional further addresses for prefetching by using multiple stride values, using feedback to adjust the training process and compensating for page table boundaries.

公开(公告)号：US10185731B2

公开(公告)日：2019-01-22

申请号：US15086866

申请日：2016-03-31

Applicant: ARM LIMITED

Inventor： Mitchell Bryan Hayenga ,  Curtis Glenn Dunham ,  Dam Sunwoo

IPC: G06F17/30 ,  G06F12/0875

Abstract: An apparatus has processing circuitry for processing instructions from multiple threads. A storage structure is shared between the threads and has a number of entries. Indexing circuitry generates a target index value identifying an entry of the storage structure to be accessed in response to a request from the processing circuitry specifying a requested index value corresponding to information to be accessed from the storage structure. The indexing circuitry generates the target index value as a function of the requested index value and a key value selected depending on which of the threads trigger the request. The key value for at least one of the threads is updated from time to time.