公开(公告)号：US11599361B2

公开(公告)日：2023-03-07

申请号：US17315737

申请日：2021-05-10

Applicant: Arm Limited

Inventor： Jaekyu Lee ,  Yasuo Ishii ,  Krishnendra Nathella ,  Dam Sunwoo

IPC: G06F9/38

Abstract: A data processing apparatus is provided. It includes control flow detection prediction circuitry that performs a presence prediction of whether a block of instructions contains a control flow instruction. A fetch queue stores, in association with prediction information, a queue of indications of the instructions and the prediction information comprises the presence prediction. An instruction cache stores fetched instructions that have been fetched according to the fetch queue. Post-fetch correction circuitry receives the fetched instructions prior to the fetched instructions being received by decode circuitry, the post-fetch correction circuitry includes analysis circuitry that causes the fetch queue to be at least partly flushed in dependence on a type of a given fetched instruction and the prediction information associated with the given fetched instruction.

公开(公告)号：US11966785B2

公开(公告)日：2024-04-23

申请号：US16943117

申请日：2020-07-30

Applicant: Arm Limited

Inventor： Dam Sunwoo ,  Supreet Jeloka ,  Saurabh Pijuskumar Sinha ,  Jaekyu Lee ,  Jose Alberto Joao ,  Krishnendra Nathella

IPC: G06F9/46 ,  G06F9/50 ,  G06N5/04 ,  G06N20/00

CPC classification number: G06F9/5044 ,  G06F9/5038 ,  G06F9/505 ,  G06N5/04 ,  G06N20/00

Abstract: A method for controlling hardware resource configuration for a processing system comprises obtaining performance monitoring data indicative of processing performance associated with workloads to be executed on the processing system, providing a trained machine learning model with input data depending on the performance monitoring data; and based on an inference made from the input data by the trained machine learning model, setting control information for configuring the processing system to control an amount of hardware resource allocated for use by at least one processor core. A corresponding method of training the model is provided. This is particularly useful for controlling inter-core borrowing of resource between processor cores in a multi-core processing system, where resource is borrowed between respective cores, e.g. cores on different layers of a 3D integrated circuit.

公开(公告)号：US10769070B2

公开(公告)日：2020-09-08

申请号：US16140625

申请日：2018-09-25

Applicant: Arm Limited

Inventor： Joseph Michael Pusdesris ,  Miles Robert Dooley ,  Alexander Cole Shulyak ,  Krishnendra Nathella ,  Dam Sunwoo

IPC: G06F12/0862 ,  G06F9/30 ,  G06F5/06

Abstract: Apparatuses and methods for prefetch generation are disclosed. Prefetching circuitry receives addresses specified by load instructions and can cause retrieval of a data value from an address before that address is received. Stride determination circuitry determines stride values as a difference between a current address and a previously received address. Plural stride values corresponding to a sequence of received addresses are determined. Multiple stride storage circuitry stores the plurality of stride values determined by the stride determination circuitry. New address comparison circuitry determines whether a current address corresponds to a matching stride value based on the plurality of stride values stored in the multiple stride storage circuitry. Prefetch initiation circuitry can causes a data value to be retrieved from a further address, wherein the further address is the current address modified by the matching stride value of the plurality of stride values. By the use of multiple stride values, more complex load address patterns can be prefetched.

公开(公告)号：US11797307B2

公开(公告)日：2023-10-24

申请号：US17355641

申请日：2021-06-23

Applicant: Arm Limited

Inventor： Krishnendra Nathella ,  David Hennah Mansell ,  Alejandro Rico Carro ,  Andrew Mundy

IPC: G06F9/30 ,  G06F9/38 ,  G06F12/12

CPC classification number: G06F9/3802 ,  G06F9/30047 ,  G06F9/3818 ,  G06F12/12 ,  G06F2212/1044 ,  G06F2212/6028

Abstract: In response to an instruction decoder decoding a range prefetch instruction specifying first and second address-range-specifying parameters and a stride parameter, prefetch circuitry controls, depending on the first and second address-range-specifying parameters and the stride parameter, prefetching of data from a plurality of specified ranges of addresses into the at least one cache. A start address and size of each specified range is dependent on the first and second address-range-specifying parameters. The stride parameter specifies an offset between start addresses of successive specified ranges. Use of the range prefetch instruction helps to improve programmability and improve the balance between prefetch coverage and circuit area of the prefetch circuitry.

公开(公告)号：US11526356B2

公开(公告)日：2022-12-13

申请号：US16887442

申请日：2020-05-29

Applicant: Arm Limited

Inventor： Lingzhe Cai ,  Krishnendra Nathella ,  Jaekyu Lee ,  Dam Sunwoo

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/54 ,  G06F12/0862 ,  G06F12/1027 ,  G06F9/52

Abstract: An apparatus and method is provided, the apparatus comprising a processor pipeline to execute instructions, a cache structure to store information for reference by the processor pipeline when executing said instructions; and prefetch circuitry to issue prefetch requests to the cache structure to cause the cache structure to prefetch information into the cache structure in anticipation of a demand request for that information being issued to the cache structure by the processor pipeline. The processor pipeline is arranged to issue a trigger to the prefetch circuitry on detection of a given event that will result in a reduced level of demand requests being issued by the processor pipeline, and the prefetch circuitry is configured to control issuing of prefetch requests in dependence on reception of the trigger.

公开(公告)号：US20240021232A1

公开(公告)日：2024-01-18

申请号：US17866448

申请日：2022-07-15

Applicant: Arm Limited

Inventor： Divya Madapusi Srinivas Prasad ,  Krishnendra Nathella ,  David Victor Pietromonaco

IPC: G11C11/406 ,  G11C11/409

CPC classification number: G11C11/40607 ,  G11C11/409

Abstract: According to one implementation of the present disclosure, a cache memory includes: a plurality of cache-lines, wherein each row of cache-lines comprises: tag bits of a tag-random access memory (tag-RAM); data bits of a data-random access memory (data-RAM), and a single set of retention bits corresponding to the tag-RAM. According to one implementation of the present disclosure, a method includes: sampling a single set of retention bits of a cache-line of a cache memory, where the cache-line comprises the single set of retention bits, tag-RAM and data-RAM, and where at least the single set of retention bits comprise eDRAM bitcells; and performing a refresh cycle of at least the data-RAM corresponding to the tag-RAM based on the sampled single set of retention bits.

公开(公告)号：US20200097409A1

公开(公告)日：2020-03-26

申请号：US16139160

申请日：2018-09-24

Applicant: Arm Limited

Inventor： Krishnendra Nathella ,  Chris Abernathy ,  Huzefa Moiz Sanjeliwala ,  Dam Sunwoo ,  Balaji Vijayan

IPC: G06F12/0862 ,  G06F9/30

Abstract: A variety of data processing apparatuses are provided in which stride determination circuitry determines a stride value as a difference between a current address and a previously received address. Stride storage circuitry stores an association between stride values determined by the stride determination circuitry and a frequency during a training period. Prefetch circuitry causes a further data value to be proactively retrieved from a further address. The further address is the current address modified by a stride value in the stride storage circuitry having a highest frequency during the training period. The variety of data processing apparatuses are directed towards improving efficiency by variously disregarding certain candidate stride values, considering additional further addresses for prefetching by using multiple stride values, using feedback to adjust the training process and compensating for page table boundaries.

公开(公告)号：US20230367843A1

公开(公告)日：2023-11-16

申请号：US17743705

申请日：2022-05-13

Applicant: Arm Limited

Inventor： Joshua Randall ,  Jesse Garrett Beu ,  Krishnendra Nathella ,  Tuan Quang Ta

IPC: G06F17/16 ,  G06F7/36 ,  G06F7/50

CPC classification number: G06F17/16 ,  G06F7/36 ,  G06F7/50

Abstract: A data processing method and processor instructions are provided that leverage scatter operations to efficiently merge vector and matrix indices, as compared to standard matrix and vector operations, as well as merge other arithmetic results, lists of numbers, etc.

公开(公告)号：US10817426B2

公开(公告)日：2020-10-27

申请号：US16139160

申请日：2018-09-24

Applicant: Arm Limited

Inventor： Krishnendra Nathella ,  Chris Abernathy ,  Huzefa Moiz Sanjeliwala ,  Dam Sunwoo ,  Balaji Vijayan

IPC: G06F12/0862 ,  G06F9/30

Abstract: A variety of data processing apparatuses are provided in which stride determination circuitry determines a stride value as a difference between a current address and a previously received address. Stride storage circuitry stores an association between stride values determined by the stride determination circuitry and a frequency during a training period. Prefetch circuitry causes a further data value to be proactively retrieved from a further address. The further address is the current address modified by a stride value in the stride storage circuitry having a highest frequency during the training period. The variety of data processing apparatuses are directed towards improving efficiency by variously disregarding certain candidate stride values, considering additional further addresses for prefetching by using multiple stride values, using feedback to adjust the training process and compensating for page table boundaries.