公开(公告)号：US06321319B2

公开(公告)日：2001-11-20

申请号：US09756304

申请日：2001-01-08

申请人： Rodney J. Drake ,  Randy L. Yach ,  Joseph W. Triece ,  Jennifer Chiao ,  Igor Wojewoda ,  Steve Allen

发明人： Rodney J. Drake ,  Randy L. Yach ,  Joseph W. Triece ,  Jennifer Chiao ,  Igor Wojewoda ,  Steve Allen

IPC分类号： G06F1202

CPC分类号： G06F9/3802 ,  G06F9/3816

摘要： A system for allowing a two word jump instruction to be executed in the same number of cycles as a single word jump instruction, thereby allowing a processor system to increase memory space without reducing performance. A first address bus is coupled to the linearized program memory for sending addresses of instructions to be fetched to a linearized program memory. A pointer is coupled to the first address bus for storing an address location of a current instruction in the linearized program memory to be fetched and for placing the address location of the current instruction to be fetched on the first address bus. A second address bus is provided and has one end coupled to the output of the program memory and a second end coupled to the first address bus. The second address bus is used for placing an address of an operand of a second word of the two word jump instruction onto the first address bus after an address of an operand of a first word of the two word jump instruction has been placed on the first address bus. This allows the addresses of the first word and the second word to be combined to provide the full address value of the two word jump instruction in the same number of cycles as a single word jump instruction.