公开(公告)号：US07170136B2

公开(公告)日：2007-01-30

申请号：US11201373

申请日：2005-08-10

申请人： Randy L. Yach ,  Greg Dix

发明人： Randy L. Yach ,  Greg Dix

IPC分类号： H01L23/62

CPC分类号： H01L27/0259

摘要： A high voltage ESD-protection structure is used to protect delicate transistor circuits connected to an input or output of an integrated circuit bond pad from destructive high voltage ESD events by conducting at a controlled breakdown voltage that is less than a voltage that may cause destructive breakdown of the input and/or output circuits. The ESD-protection structure is able to absorb high current from these ESD events without snapback that would compromise operation of the higher voltage inputs and/or outputs of the integrated circuit. The ESD-protection structure will conduct when an ESD event occurs at a voltage above a controlled breakdown voltage of an electronic device, e.g., diode, in the ESD protection structure. Conduction of current from an ESD event having a voltage above the electronic device controlled breakdown voltage may be through another electronic device, e.g., transistor, having high current conduction capabilities, in the ESD-protection structure that may be controlled (triggered) by the device (e.g., diode) determining the controlled breakdown voltage (at which the ESD voltage is clamped to a desired value). The high voltage ESD-protection structure may be located substantially under the bond pad and may also include a low capacitance forward diode structure between the bond pad and the ESD clamp circuit.

公开(公告)号：US07002218B2

公开(公告)日：2006-02-21

申请号：US10787387

申请日：2004-02-26

申请人： Randy L. Yach

发明人： Randy L. Yach

IPC分类号： H01L23/62

CPC分类号： H01L27/0259 ,  Y10S257/917

摘要： An ESD-protection structure is located substantially under an integrated circuit bond pad. This ESD-protection structure is formed as a low capacitance structure by inserting a forward diode between the bond pad and the ESD clamp circuit. Placing the ESD-protection structure under the bond pad eliminates parasitic substrate capacitance and utilizes a parasitic PNP transistor formed from the inserted forward biased diode. The ESD-protection structure includes adjacent alternating P+ and N+ diffusions located substantially under a bond pad to be ESD protected. The P+ diffusions are connected to the bond pad metal with metal vias through an insulating layer. The N+ diffusions are adjacent to the P+ diffusions. An N+ diffusion surrounds the N+ and P+ diffusions, and ties together the N+ diffusions so as to form a continuous N+ diffusion completely around each of the P+ diffusions. An N− well is located substantially under the N+ and P+ diffusions. The surrounding N+ diffusion partially overlaps the edge of the N− well below it. An outer portion of the N+ diffusion, the portion overlapping the N− well, is within a P− well. Another N+ diffusion encircles the N+ diffusion surrounding the P+ diffusions. The another N+ diffusion is in the P− well and a field oxide may be located between the N+ diffusion and the another N+ diffusion. An NPN field transistor is formed with the N+ diffusion being the transistor collector, the P− well being the transistor base and the another N+ diffusion being the emitter.

摘要翻译： ESD保护结构基本上位于集成电路接合焊盘下方。 该ESD保护结构通过在接合焊盘和ESD钳位电路之间插入正向二极管而形成为低电容结构。 将ESD保护结构放在接合焊盘下方可消除寄生衬底电容，并利用由插入的正向偏置二极管形成的寄生PNP晶体管。 ESD保护结构包括基本上位于接合焊盘下方以进行ESD保护的相邻的交替P +和N +扩散。 P +扩散通过绝缘层与金属通孔连接到接合焊盘金属。 N +扩散与P +扩散相邻。 N +扩散围绕N +和P +扩散，并将N +扩散结合在一起，以便在每个P +扩散周围完全形成连续的N +扩散。 N阱基本上位于N +和P +扩散之下。 周围的N +扩散与其下面的N阱的边缘部分重叠。 N +扩散的外部部分，与N阱重叠的部分在P-阱内。 另外N +扩散围绕围绕P +扩散的N +扩散。 另一个N +扩散在P-阱中，场氧化物可以位于N +扩散和另一个N +扩散之间。 形成NPN场晶体管，其中N +扩散为晶体管集电极，P阱为晶体管基极，另一N +扩散为发射极。

公开(公告)号：US06208500B1

公开(公告)日：2001-03-27

申请号：US09200542

申请日：1998-11-25

申请人： Sam E. Alexander ,  Randy L. Yach ,  Roger St. Amand

发明人： Sam E. Alexander ,  Randy L. Yach ,  Roger St. Amand

IPC分类号： H01G4005

CPC分类号： H01L28/40 ,  H01L27/0805

摘要： An improved high quality factor capacitive device is implemented on a single, monolithic integrated circuit. The new layout techniques improve the quality factor (Q) of the capacitor by reducing intrinsic resistance of the capacitor by reducing the distance between the metal contacts of the top and bottom conductive plates. The layout techniques require laying out the top conductive plate of the capacitor in strips such that metal contacts from the bottom conductive plate pass in between the strips and through the dielectric layer. Alternatively, the apertures may be etched into the top conductive plate so that metal contacts pass through the apertures and connect to the bottom conductive plate.

摘要翻译： 改进的高品质因素电容器件在单个单片集成电路上实现。 新的布局技术通过减小顶部和底部导电板的金属触点之间的距离来降低电容器的固有电阻，从而提高了电容器的品质因数（Q）。 布局技术需要将带状电容器的顶部导电板布置成使得来自底部导电板的金属接触通过条带之间并通过介电层。 或者，孔可以被蚀刻到顶部导电板中，使得金属触点穿过孔并连接到底部导电板。

公开(公告)号：US5835410A

公开(公告)日：1998-11-10

申请号：US871340

申请日：1997-06-09

申请人： Randy L. Yach ,  Richard L. Hull

发明人： Randy L. Yach ,  Richard L. Hull

IPC分类号： G11C16/02 ,  G11C7/06 ,  G11C16/06

CPC分类号： G11C7/067

摘要： A self timed precharge sense amplifier for allowing high speed reading of a memory cell of a memory array. The self timed precharge sense amplifier uses a precharge device for generating an output voltage which is used to ramp up a voltage level of a column of the memory array where the memory cell is located. State control circuitry is coupled to the precharge device for activating and deactivating the precharge device. A sense amplifier is coupled to the precharge device and to the state control circuitry for monitoring the output voltage of the precharge device and for signalling the state control circuitry to deactivate the precharge device when the output voltage has reached a threshold voltage level set by the sense amplifier which is a minimum amount of voltage required to properly read the memory cell.

摘要翻译： 一种用于允许存储器阵列的存储单元的高速读取的自定时预充电读出放大器。 自定时预充电读出放大器使用预充电装置来产生用于使存储器单元所在的存储器阵列的列的电压电平升高的输出电压。 状态控制电路耦合到预充电装置，用于激活和去激活预充电装置。 感测放大器耦合到预充电装置和状态控制电路，用于监视预充电装置的输出电压，并且当输出电压达到由感测设定的阈值电压电平时，用于发信号通知状态控制电路去激活预充电装置 放大器，其是正确读取存储器单元所需的最小电压量。

公开(公告)号：US5815445A

公开(公告)日：1998-09-29

申请号：US866359

申请日：1997-05-30

申请人： Richard L. Hull ,  Randy L. Yach

发明人： Richard L. Hull ,  Randy L. Yach

IPC分类号： G11C5/14 ,  G11C16/30 ,  G11C7/00

CPC分类号： G11C5/147 ,  G11C16/30

摘要： A voltage regulator which will clamp the row voltage of a memory cell or array. The voltage regulator will clamp to a value which is greater than the erased threshold voltage of the memory cell and less than the worst case programmed threshold voltage of the memory cell. The voltage regulator uses an unprogrammed memory cell of the memory array for allowing the row voltage outputted by the voltage regulator to be self-tracking over manufacturing process variations and ambient environmental influences. A switching circuit is coupled to the unprogrammed memory cell for clamping the row voltage outputted by said voltage regulator below the programmed threshold voltage level.

摘要翻译： 将钳位存储单元或阵列的行电压的电压调节器。 电压调节器将钳位到大于存储器单元的擦除阈值电压的值，并且小于存储器单元的最坏情况编程的阈值电压。 电压调节器使用存储器阵列的未编程的存储单元，以允许电压调节器输出的行电压自动跟踪制造工艺变化和环境环境影响。 开关电路耦合到未编程的存储单元，用于将由所述电压调节器输出的行电压钳位在编程的阈值电压电平以下。

公开(公告)号：US5606511A

公开(公告)日：1997-02-25

申请号：US368919

申请日：1995-01-05

申请人： Randy L. Yach

发明人： Randy L. Yach

IPC分类号： G01R19/165 ,  G06F1/24 ,  G06F1/28 ,  G06F1/30 ,  G06F11/30 ,  G06F15/78 ,  H02H3/247 ,  G01R19/00

CPC分类号： H02H3/247

摘要： A microcontroller device is fabricated in a semiconductor integrated circuit chip to control an external system with which the device is to be installed in circuit. The device has a CPU, a program memory for storing program instructions to be implemented by the CPU, a data memory for storing data including data pertaining to parameters of the external system to be controlled by operation of the CPU according to the instructions, and various peripherals. A brown-out protection circuit monitors the level of the supply voltage for the IC chip relative to a ground reference level, to reset the device as protection against its malfunction in response to reduction of an arithmetic difference between the supply voltage level and the ground reference level to a value less than a predetermined threshold operating voltage level. Reset defines a cessation of operation of the device while maintaining status quo of implementation of program instructions by the CPU and data stored in the data memory. A discriminator distinguishes between a reduction representative of a brown-out event warranting invoking a reset of the device and a reduction representative of mere transitory voltage swings commonly occurring in the device operation not warranting invoking a reset of the device. This serves to avoid both malfunctions and unnecessary resetting of the device in control of the external system.

摘要翻译： 在半导体集成电路芯片中制造微控制器装置，以控制将该装置安装在电路中的外部系统。 该装置具有CPU，用于存储要由CPU实现的程序指令的程序存储器，用于存储包括根据指令通过CPU的操作来控制的外部系统的参数的数据的数据的数据存储器，以及各种 外设。 欠压保护电路监控IC芯片相对于接地参考电平的电源电压的电平，以响应于减小电源电压电平和接地参考之间的算术差异来复位器件以防止其故障 电平达到小于预定阈值工作电压电平的值。 复位定义了设备的操作停止，同时保持CPU和存储在数据存储器中的数据实现程序指令的状态。 鉴别器区分降低代表性，以减少调用设备复位的欠压事件，以及减少代表在设备操作中通常发生的短暂的电压摆幅，这不意味着调用设备的复位。 这用于在外部系统的控制中避免故障和设备的不必要的重置。

公开(公告)号：US06593639B2

公开(公告)日：2003-07-15

申请号：US09846018

申请日：2001-04-30

申请人： Randy L. Yach ,  Igor Wojewoda

发明人： Randy L. Yach ,  Igor Wojewoda

IPC分类号： H01L2900

CPC分类号： H01L27/0805

摘要： A matching capacitor array is implemented on a single, monolithic integrated circuit. The array features a matrix of bottom electrodes and a plurality of continuous top electrode strips, where each continuous top electrode strip spans numerous bottom electrodes. The conductive contacts for each continuous top electrode strip are removed from the capacitor interface to the terminal ends of each of the continuous top electrode strips. The invention seeks to match or control parasitic and fringe capacitance, rather than to eliminate or minimize such capacitances. By creating a matched array, the parasitic and fringe capacitances of each matching capacitor unit cell are incorporated into the total capacitance of the unit cell.

摘要翻译： 匹配的电容器阵列在单个单片集成电路上实现。 该阵列具有底部电极矩阵和多个连续顶部电极条，其中每个连续顶部电极条跨越多个底部电极。 每个连续顶部电极条的导电触点从电容器接口移除到每个连续顶部电极条的末端。 本发明寻求匹配或控制寄生和边缘电容，而不是消除或最小化这种电容。 通过创建匹配的阵列，每个匹配电容器单元的寄生和边缘电容被并入到单元的总电容中。

公开(公告)号：US06300183B1

公开(公告)日：2001-10-09

申请号：US09272675

申请日：1999-03-19

申请人： Donald S. Gerber ,  Randy L. Yach ,  Kent D. Hewitt ,  Gianpaolo Spadini

发明人： Donald S. Gerber ,  Randy L. Yach ,  Kent D. Hewitt ,  Gianpaolo Spadini

IPC分类号： H01L218238

CPC分类号： H01L27/11521 ,  G11C16/0416 ,  H01L27/0207 ,  H01L27/11519

摘要： An array of P-channel memory cells is separated into independently programmable memory segments by creating multiple, electrically isolated N-wells upon which the memory segments are fabricated. The methods for creating the multiple, electrically isolated N-wells include p-n junction isolation and dielectric isolation.

摘要翻译： 通过产生多个电隔离的N阱，将P阵列的P沟道存储单元分成独立的可编程存储器段，在其上制造存储器段。 用于产生多个电隔离的N阱的方法包括p-n结隔离和介电隔离。

公开(公告)号：US06243798B1

公开(公告)日：2001-06-05

申请号：US08958940

申请日：1997-10-28

申请人： Rodney J. Drake ,  Randy L. Yach ,  Joseph W. Triece ,  Jennifer Chiao ,  Igor Wojewoda ,  Steve Allen

发明人： Rodney J. Drake ,  Randy L. Yach ,  Joseph W. Triece ,  Jennifer Chiao ,  Igor Wojewoda ,  Steve Allen

IPC分类号： G06F1202

CPC分类号： G06F9/3802 ,  G06F9/3816

摘要： A system for allowing a two word jump instruction to be executed in the same number of cycles as a single word jump instruction, thereby allowing a processor system to increase memory space without reducing performance. A first address bus is coupled to the linearized program memory for sending addresses of instructions to be fetched to a linearized program memory. A pointer is coupled to the first address bus for storing an address location of a current instruction in the linearized program memory to be fetched and for placing the address location of the current instruction to be fetched on the first address bus. A second address bus is provided and has one end coupled to the output of the program memory and a second end coupled to the first address bus. The second address bus is used for placing an address of an operand of a second word of the two word jump instruction onto the first address bus after an address of an operand of a first word of the two word jump instruction has been placed on the first address bus. This allows the addresses of the first word and the second word to be combined to provide the full address value of the two word jump instruction in the same number of cycles as a single word jump instruction.

摘要翻译： 用于允许以与单个字跳转指令相同的周期数来执行两个字跳转指令的系统，从而允许处理器系统增加存储器空间而不降低性能。 第一地址总线耦合到线性化程序存储器，用于发送要获取的指令的地址到线性化程序存储器。 指针耦合到第一地址总线，用于存储要获取的线性化程序存储器中的当前指令的地址位置，并将要提取的当前指令的地址位置放置在第一地址总线上。 提供第二地址总线，其一端耦合到程序存储器的输出端，第二端耦合到第一地址总线。 第二地址总线用于在双字跳转指令的第一字的操作数的地址已经被放置在第一地址总线上之后，将两字跳转指令的第二字的操作数的地址放置在第一地址总线上 地址总线 这允许将第一个字和第二个字的地址组合起来，以与单个字跳转指令相同的周期数来提供两个字跳转指令的完整地址值。

公开(公告)号：US06198691B1

公开(公告)日：2001-03-06

申请号：US09513427

申请日：2000-02-25

申请人： Randy L. Yach

发明人： Randy L. Yach

IPC分类号： G11C800

CPC分类号： G06F12/0623 ,  G06F9/30098 ,  G06F9/30185 ,  G06F9/34 ,  H02J13/0027

摘要： A microcontroller architecture that adds a dedicated bit in the op-code decode field to force data access to take place on a page of the random access memory (RAM) for that instruction. This allows the user to have any page selected and still have direct access to the special function registers or the register variables that are located on a pre-defined page of the RAM. The setting of the dedicated bit will not affect the current operation of the microcontroller nor will the setting of the bit modify the currently selected address stored in a page select register currently being used by the microcontroller.