公开(公告)号：US11921240B2

公开(公告)日：2024-03-05

申请号：US17025927

申请日：2020-09-18

Applicant: BFLY OPERATIONS, INC.

Inventor： Kailiang Chen ,  Daniel Rea McMahill ,  Joseph Lutsky ,  Keith G. Fife ,  Nevada J. Sanchez

IPC: G01S7/52

CPC classification number: G01S7/52025 ,  G01S7/52017 ,  G01S7/5202 ,  G01S7/52022 ,  G01S7/52085

Abstract: Circuitry for an ultrasound device is described. The ultrasound device may include a symmetric switch positioned between a pulser and an ultrasound transducer. The pulser may produce bipolar pulses. The symmetric switch may selectively isolate a receiver from the pulser and the ultrasound transducer during a transmit mode of the device, when the bipolar pulses are provided by the pulser to the ultrasound transducer for transmission, and may selectively permit the receiver to receive signals from the ultrasound transducer during a receive mode. The symmetric switch may be provided with a well switch to remove well capacitances in a signal path of the device.

公开(公告)号：US11375980B2

公开(公告)日：2022-07-05

申请号：US16404672

申请日：2019-05-06

Applicant: BFLY Operations, Inc.

Inventor： Kailiang Chen ,  Nevada J. Sanchez ,  Susan A. Alie ,  Tyler S. Ralston ,  Jonathan M. Rothberg ,  Keith G. Fife ,  Joseph Lutsky

IPC: H04B1/06 ,  A61B8/08 ,  H04B11/00 ,  A61B8/00

Abstract: Aspects of the technology described herein relate to an ultrasound device including a first die that includes an ultrasonic transducer, a first application-specific integrated circuit (ASIC) that is bonded to the first die and includes a pulser, and a second ASIC in communication with the second ASIC that includes integrated digital receive circuitry. In some embodiments, the first ASIC may be bonded to the second ASIC and the second ASIC may include analog processing circuitry and an analog-to-digital converter. In such embodiments, the second ASIC may include a through-silicon via (TSV) facilitating communication between the first ASIC and the second ASIC. In some embodiments, SERDES circuitry facilitates communication between the first ASIC and the second ASIC and the first ASIC includes analog processing circuitry and an analog-to-digital converter. In some embodiments, the technology node of the first ASIC is different from the technology node of the second ASIC.