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公开(公告)号：US20200005881A1
公开(公告)日：2020-01-02
申请号：US16489185
申请日：2018-10-25
Inventor： Peng LIU , Zhen WANG , Han ZHANG , Kai ZHANG , Yun QIAO , Jian SUN , Bailing LIU , Fei HUANG , Zhengkui WANG , Jianjun ZHANG
IPC: G11C19/28 , G09G3/36 , G09G3/3266
Abstract: A shift register includes a first input sub-circuit, a pull-up control sub-circuit, and a pull-down control sub-circuit. The first input sub-circuit is configured to transmit a voltage from the first signal terminal to the first node under control of the first voltage terminal. The pull-up control sub-circuit is configured to be in a turn-on or turn-off state under control of the first node. The pull-down control sub-circuit is configured to transmit a voltage from the third voltage terminal to the pull-down node under control of the first node, transmit the voltage from the third voltage terminal to the pull-down node under control of the signal output terminal, and transmit a voltage from the first clock signal terminal to the pull-down node under control of the first clock signal terminal.
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公开(公告)号：US20190301001A1
公开(公告)日：2019-10-03
申请号：US16179455
申请日：2018-11-02
Inventor： JIAN ZHANG , Chunchieh HUANG , Zhiming LIN , Zhen WANG
Abstract: A metal mask includes a mask body part and two connecting parts disposed at opposite sides of the mask body part. Each of the connecting parts includes a body portion and a single-stage step portion. A side of the body portion is connected to the mask body part, and an opposite side of the body portion is connected to the single-stage step portion. A thickness of the single-stage step portion is smaller than a thickness of the body portion.
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公开(公告)号：US20190288009A1
公开(公告)日：2019-09-19
申请号：US16352379
申请日：2019-03-13
Inventor： Yun QIAO , Zhen WANG , Lele CONG , Zhengkui WANG , Jianjun ZHANG , Han ZHANG , Wenwen QIN , Fei HUANG , Xiaozhou ZHAN , Peng LIU , Jian SUN
IPC: H01L27/12
Abstract: A display panel and a display device are provided. The display panel includes a base substrate, the base substrate includes a display region and a non-display region, the display region includes a main display region and a peripheral display region, and the peripheral display region includes an irregular display region; the non-display region includes a first region and a second region, the first region is adjacent to the irregular display region, and the second region is adjacent to other regions of the peripheral display region than the irregular display region; the display region includes at least one signal line, the non-display region includes at least one functional circuit and at least one wire, and the at least one functional circuit is coupled to the at least one signal line via the at least one wire.
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公开(公告)号：US20190010600A1
公开(公告)日：2019-01-10
申请号：US15745038
申请日：2017-07-03
Inventor： Zhiming LIN , Zhen WANG , Jian ZHANG
Abstract: The present disclosure provides a mask body, including at least one mask area and a non-mask area surrounding the at least one mask area. A portion, directly facing the mask area, of an edge extending along a preset stretching direction of the mask body is a curved portion. The curved portion recesses towards the mask area that the curved portion directly faces. Accordingly, the present disclosure further provides a mask and a fabrication method thereof. The present disclosure can alleviate wrinkle phenomenon on both sides of a mask area of a mask.
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公开(公告)号：US20180196341A1
公开(公告)日：2018-07-12
申请号：US15798753
申请日：2017-10-31
Inventor： Zhiming LIN , Zhen WANG
Abstract: A method of preparing a mask, a mask and an evaporation system are provided. The mask includes a frame having an opening in a middle region thereof and a mask pattern disposed above the frame. The method of preparing the mask includes: applying first opposite forces to the frame during a molding process of the frame; applying second opposite forces to the frame, during a welding process when the mask pattern is welded to at least part of the frame to cover an inner opening region of the frame; wherein the first opposite forces and the second opposite forces are equal in magnitude and the same in direction.
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Patent Agency Ranking
16.发明申请公开(公告)号：US20140206139A1
公开(公告)日：2014-07-24
申请号：US14106658
申请日：2013-12-13
Inventor： Shuibin NI , Zhen WANG
CPC classification number: H01L27/1225 , H01L27/1288 , H01L29/66969 , H01L29/7869
Abstract: The present invention provides methods for fabricating a thin film transistor and an array substrate, which are applicable in the field of display device fabrication, and solve the problem of performing patterning process too many times during the fabrications of a thin film transistor and an array substrate. The method for fabricating a thin film transistor comprises: forming a gate layer on a substrate; forming a gate insulation layer on the substrate; forming an oxide semiconductor layer and a barrier layer and on the substrate; and forming a source-drain layer on the substrate, wherein, the step of forming the oxide semiconductor layer and the barrier layer comprises: sequentially forming an oxide semiconductor film a the barrier film; and forming the oxide semiconductor layer from the oxide semiconductor film and the barrier layer from the barrier film by performing a patterning process once.
Abstract translation: 本发明提供了可应用于显示装置制造领域的薄膜晶体管和阵列基板的制造方法，解决了在薄膜晶体管和阵列基板的制造过程中进行图案化处理太多次的问题 。 制造薄膜晶体管的方法包括：在衬底上形成栅极层; 在所述基板上形成栅极绝缘层; 在所述基板上形成氧化物半导体层和阻挡层; 以及在所述衬底上形成源极 - 漏极层，其中形成所述氧化物半导体层和所述势垒层的步骤包括：顺序地形成所述阻挡膜的氧化物半导体膜; 并且通过进行一次图案化处理，从氧化物半导体膜和阻挡层形成氧化物半导体层。
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公开(公告)号：US20240419458A1
公开(公告)日：2024-12-19
申请号：US18703728
申请日：2023-05-06
Applicant: BOE Technology Group Co., Ltd.
Inventor： Zhen WANG
Abstract: Provided in the embodiments of the present disclosure are an algorithm running method, apparatus and device, and a storage medium. The algorithm operation method comprises: acquiring grouping information of a plurality of groups of target algorithms; and running the plurality of groups of target algorithms on a plurality of data processing devices according to the grouping information of the plurality of groups of target algorithms, wherein target algorithms corresponding to the same group of grouping information run on the same data processing device.
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公开(公告)号：US20240276809A1
公开(公告)日：2024-08-15
申请号：US18564071
申请日：2021-05-27
Inventor： Yuanjie XU , Benlian WANG , Zhenli ZHOU , Zhiming REN , Xiaofeng YANG , Zhen WANG , Zhong LU , Lili DU , Donghua JIANG
IPC: H10K59/131 , H10K59/12
CPC classification number: H10K59/131 , H10K59/1201
Abstract: Embodiments of the present disclosure provide a display substrate, a method for manufacturing the display substrate, and a display device. The display substrate includes: a base substrate having a wiring area; at least one wiring layer located on the base substrate, and each wiring layer includes a plurality of first wires and a plurality of second wires, which are arranged at intervals and obtained by adopting different patterning processes, in the wiring area, at least part of the first wires are arranged adjacent to the second wires, and a space between the first wire and the second wire adjacent to each other is less than 2 μm.
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19.发明申请公开(公告)号：US20210336104A1
公开(公告)日：2021-10-28
申请号：US16320163
申请日：2018-05-11
Inventor： Zhen WANG , Haiwei SUN , Jian SANG , Junjie MA , Shubai ZHANG , Zhonghua LI
Abstract: A light source structure, an electronic device and a manufacturing method of a light source structure are disclosed. The light source structure includes a light-emitting unit, a printed circuit board and a bonding layer. The light-emitting unit includes a substrate and at least one light-emitting element on the substrate. The printed circuit board includes a first surface, and the light-emitting unit is disposed on the first surface of the printed circuit board via the substrate. The bonding layer is disposed between the substrate and the first surface of the printed circuit board, and for adhesively bonding the substrate and the printed circuit board together.
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公开(公告)号：US20210335193A1
公开(公告)日：2021-10-28
申请号：US16323406
申请日：2018-05-31
IPC: G09G3/20
Abstract: A shift register unit, a driving device, a display device and a driving method are provided. The shift register unit includes an input circuit, a first pull-up node reset circuit, an output circuit, an output reset circuit, a pull-down node control circuit and a power-on initialization circuit. The power-on initialization circuit is configured to reset the pull-up node in response to a power-on initialization signal.
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