Programmable graphics processor for multithreaded execution of programs
    11.
    发明授权
    Programmable graphics processor for multithreaded execution of programs 有权
    用于多线程执行程序的可编程图形处理器

    公开(公告)号:US08405665B2

    公开(公告)日:2013-03-26

    申请号:US13466043

    申请日:2012-05-07

    CPC分类号: G06T15/005

    摘要: A processing unit includes multiple execution pipelines, each of which is coupled to a first input section for receiving input data for pixel processing and a second input section for receiving input data for vertex processing and to a first output section for storing processed pixel data and a second output section for storing processed vertex data. The processed vertex data is rasterized and scan converted into pixel data that is used as the input data for pixel processing. The processed pixel data is output to a raster analyzer.

    摘要翻译: 处理单元包括多个执行流水线,每个执行流水线连接到第一输入部分,用于接收用于像素处理的输入数据和用于接收用于顶点处理的输入数据的第二输入部分和用于存储经处理的像素数据的第一输出部分和 用于存储经处理的顶点数据的第二输出部分。 经处理的顶点数据被光栅化并扫描转换为用作像素处理的输入数据的像素数据。 经处理的像素数据被输出到光栅分析器。

    PROGRAMMABLE GRAPHICS PROCESSOR FOR MULTITHREADED EXECUTION OF PROGRAMS
    12.
    发明申请
    PROGRAMMABLE GRAPHICS PROCESSOR FOR MULTITHREADED EXECUTION OF PROGRAMS 有权
    可编程图形处理程序,用于多方案执行程序

    公开(公告)号:US20120218267A1

    公开(公告)日:2012-08-30

    申请号:US13466043

    申请日:2012-05-07

    IPC分类号: G06T17/20 G06T1/20 G06T1/00

    CPC分类号: G06T15/005

    摘要: A processing unit includes multiple execution pipelines, each of which is coupled to a first input section for receiving input data for pixel processing and a second input section for receiving input data for vertex processing and to a first output section for storing processed pixel data and a second output section for storing processed vertex data. The processed vertex data is rasterized and scan converted into pixel data that is used as the input data for pixel processing. The processed pixel data is output to a raster analyzer.

    摘要翻译: 处理单元包括多个执行流水线,每个执行流水线连接到第一输入部分,用于接收用于像素处理的输入数据和用于接收用于顶点处理的输入数据的第二输入部分和用于存储经处理的像素数据的第一输出部分和 用于存储经处理的顶点数据的第二输出部分。 经处理的顶点数据被光栅化并扫描转换为用作像素处理的输入数据的像素数据。 经处理的像素数据被输出到光栅分析器。

    OPERAND COLLECTOR ARCHITECTURE
    13.
    发明申请
    OPERAND COLLECTOR ARCHITECTURE 有权
    操作收集架构

    公开(公告)号:US20080109611A1

    公开(公告)日:2008-05-08

    申请号:US11555649

    申请日:2006-11-01

    IPC分类号: G06F13/00

    摘要: An apparatus and method for simulating a multi-ported memory using lower port count memories as banks. A collector units gather source operands from the banks as needed to process program instructions. The collector units also gather constants that are used as operands. When all of the source operands needed to process a program instruction have been gathered, a collector unit outputs the source operands to an execution unit while avoiding writeback conflicts to registers specified by the program instruction that may be accessed by other execution units.

    摘要翻译: 一种使用较低端口计数存储器作为存储体来模拟多端口存储器的装置和方法。 收集器单元根据需要从银行收集源操作数,以处理程序指令。 收集器单元还收集用作操作数的常量。 当收集处理程序指令所需的所有源操作数时,收集器单元将源操作数输出到执行单元,同时避免与由其他执行单元访问的程序指令指定的寄存器的写回冲突。

    A Programmable Graphics Processor For Multithreaded Execution of Programs
    14.
    发明申请
    A Programmable Graphics Processor For Multithreaded Execution of Programs 有权
    用于多线程执行程序的可编程图形处理器

    公开(公告)号:US20080024506A1

    公开(公告)日:2008-01-31

    申请号:US11458633

    申请日:2006-07-19

    IPC分类号: G06T1/20

    摘要: A processing unit includes multiple execution pipelines, each of which is coupled to a first input section for receiving input data for pixel processing and a second input section for receiving input data for vertex processing and to a first output section for storing processed pixel data and a second output section for storing processed vertex data. The processed vertex data is rasterized and scan converted into pixel data that is used as the input data for pixel processing. The processed pixel data is output to a raster analyzer.

    摘要翻译: 处理单元包括多个执行流水线,每个执行流水线连接到第一输入部分,用于接收用于像素处理的输入数据和用于接收用于顶点处理的输入数据的第二输入部分和用于存储经处理的像素数据的第一输出部分和 用于存储经处理的顶点数据的第二输出部分。 经处理的顶点数据被光栅化并扫描转换为用作像素处理的输入数据的像素数据。 经处理的像素数据被输出到光栅分析器。

    Programmable graphics processor for multithreaded execution of programs
    15.
    发明授权
    Programmable graphics processor for multithreaded execution of programs 有权
    用于多线程执行程序的可编程图形处理器

    公开(公告)号:US08174531B1

    公开(公告)日:2012-05-08

    申请号:US12649201

    申请日:2009-12-29

    CPC分类号: G06T15/005

    摘要: A processing unit includes multiple execution pipelines, each of which is coupled to a first input section for receiving input data for pixel processing and a second input section for receiving input data for vertex processing and to a first output section for storing processed pixel data and a second output section for storing processed vertex data. The processed vertex data is rasterized and scan converted into pixel data that is used as the input data for pixel processing. The processed pixel data is output to a raster analyzer.

    摘要翻译: 处理单元包括多个执行流水线,每个执行流水线连接到第一输入部分,用于接收用于像素处理的输入数据和用于接收用于顶点处理的输入数据的第二输入部分和用于存储经处理的像素数据的第一输出部分和 用于存储经处理的顶点数据的第二输出部分。 经处理的顶点数据被光栅化并扫描转换为用作像素处理的输入数据的像素数据。 经处理的像素数据被输出到光栅分析器。

    Using a pixel offset for evaluating a plane equation
    16.
    发明授权
    Using a pixel offset for evaluating a plane equation 有权
    使用像素偏移来评估平面方程

    公开(公告)号:US09058672B2

    公开(公告)日:2015-06-16

    申请号:US12898537

    申请日:2010-10-05

    IPC分类号: G06K9/32 G06T3/40

    CPC分类号: G06T3/4007

    摘要: One embodiment of the present invention sets forth a technique controlling the pixel location at which the plane equation is evaluated. Multiple pixel offsets (dx, dy) may be specified that each define to a sub-pixel sample position. Attributes are then calculated for each sub-pixel sample position that is covered by a geometric primitive. One advantage of the technique is that anti-aliasing quality may be improved since high frequency color components may be selectively supersampled for particular geometric primitives.

    摘要翻译: 本发明的一个实施例提出了一种控制平面方程被评估的像素位置的技术。 可以指定多个像素偏移(dx,dy),每个像素偏移定义为子像素采样位置。 然后对由几何图元覆盖的每个子像素样本位置计算属性。 该技术的一个优点是可以改善抗混叠质量,因为可以对特定几何基元选择性地超采样高频彩色分量。

    Reordering operands assigned to each one of read request ports concurrently accessing multibank register file to avoid bank conflict
    17.
    发明授权
    Reordering operands assigned to each one of read request ports concurrently accessing multibank register file to avoid bank conflict 有权
    对分配给每个读取请求端口的操作数重新排序并发访问多银行寄存器文件以避免银行冲突

    公开(公告)号:US08533435B2

    公开(公告)日:2013-09-10

    申请号:US12875843

    申请日:2010-09-03

    IPC分类号: G06F9/34

    摘要: One embodiment of the present invention sets forth a technique for collecting operands specified by an instruction. As a sequence of instructions is received the operands specified by the instructions are assigned to ports, so that each one of the operands specified by a single instruction is assigned to a different port. Reading of the operands from a multi-bank register file is scheduled by selecting an operand from each one of the different ports to produce an operand read request and ensuring that two or more of the selected operands are not stored in the same bank of the multi-bank register file. The operands specified by the operand read request are read from the multi-bank register file in a single clock cycle. Each instruction is then executed as the operands specified by the instruction are read from the multi-bank register file and collected over one or more clock cycles.

    摘要翻译: 本发明的一个实施例提出了一种用于收集由指令指定的操作数的技术。 由于接收到指令序列,指令指定的操作数被分配给端口,以便将由单个指令指定的每个操作数分配给不同的端口。 通过从不同端口中的每一个选择一个操作数来调度来自多存储器寄存器文件的操作数,以产生操作数读取请求,并确保所选择的操作数中的两个或更多个不存储在多个存储区的同一个存储区中 银行寄存器文件。 由操作数读取请求指定的操作数在单个时钟周期内从多存储体寄存器文件读取。 然后由指令指定的操作数从多存储寄存器文件中读取并在一个或多个时钟周期内采集,执行每条指令。

    Multipurpose arithmetic functional unit
    18.
    发明授权
    Multipurpose arithmetic functional unit 有权
    多功能算术功能单元

    公开(公告)号:US08190669B1

    公开(公告)日:2012-05-29

    申请号:US10970253

    申请日:2004-10-20

    IPC分类号: G06F7/44

    摘要: Multipurpose arithmetic functional units can perform planar attribute interpolation and unary function approximation operations. In one embodiment, planar interpolation operations for coordinates (x, y) are executed by computing A*x+B*y+C, and unary function approximation operations for operand x are executed by computing F2(xb)*xh2+F1(xb)*xh+F0(xb), where xh=x−xb. Shared multiplier and adder circuits are advantageously used to implement the product and sum operations for both classes of operations.

    摘要翻译: 多用途算术功能单元可以执行平面属性插值和一元函数近似运算。 在一个实施例中,通过计算A * x + B * y + C来执行坐标(x,y)的平面内插操作,并且通过计算F2(xb)* xh2 + F1(xb)来执行操作数x的一元函数近似运算 )* xh + F0(xb),其中xh = x-xb。 共享乘法器和加法器电路有利地用于实现两类操作的乘积和求和运算。

    Multipurpose functional unit with single-precision and double-precision operations
    19.
    发明授权
    Multipurpose functional unit with single-precision and double-precision operations 有权
    具有单精度和双精度运算功能的多用途功能单元

    公开(公告)号:US08037119B1

    公开(公告)日:2011-10-11

    申请号:US11359353

    申请日:2006-02-21

    IPC分类号: G06F7/44

    摘要: A multipurpose arithmetic functional unit selectably performs planar attribute interpolation, unary function approximation, and double-precision arithmetic. In one embodiment, planar interpolation operations for coordinates (x, y) are executed by computing A*x+B*y+C, and unary function approximation operations for operand x are executed by computing F2(xb)*xh2+F1(xb)*xh+F0(xb), where xh=x−xb. Shared multiplier and adder circuits are advantageously used to implement the product and sum operations for unary function approximation and planar interpolation; the same multipliers and adders are also leveraged to implement double-precision multiplication and addition.

    摘要翻译: 多用途算术功能单元可选地执行平面属性插值,一元函数近似和双精度算术。 在一个实施例中,通过计算A * x + B * y + C来执行坐标(x,y)的平面内插操作,并且通过计算F2(xb)* xh2 + F1(xb)来执行操作数x的一元函数近似运算 )* xh + F0(xb),其中xh = x-xb。 共享乘法器和加法器电路有利地用于实现一元函数近似和平面内插的乘积和求和运算; 同样的乘法器和加法器也被用来实现双精度乘法和加法。

    Unified Collector Structure for Multi-Bank Register File
    20.
    发明申请
    Unified Collector Structure for Multi-Bank Register File 有权
    多银行登记册统一采集器结构

    公开(公告)号:US20110072243A1

    公开(公告)日:2011-03-24

    申请号:US12875843

    申请日:2010-09-03

    IPC分类号: G06F9/30

    摘要: One embodiment of the present invention sets forth a technique for collecting operands specified by an instruction. As a sequence of instructions is received the operands specified by the instructions are assigned to ports, so that each one of the operands specified by a single instruction is assigned to a different port. Reading of the operands from a multi-bank register file is scheduled by selecting an operand from each one of the different ports to produce an operand read request and ensuring that two or more of the selected operands are not stored in the same bank of the multi-bank register file. The operands specified by the operand read request are read from the multi-bank register file in a single clock cycle. Each instruction is then executed as the operands specified by the instruction are read from the multi-bank register file and collected over one or more clock cycles.

    摘要翻译: 本发明的一个实施例提出了一种用于收集由指令指定的操作数的技术。 由于接收到指令序列,指令指定的操作数被分配给端口,以便将由单个指令指定的每个操作数分配给不同的端口。 通过从不同端口中的每一个选择一个操作数来调度来自多存储器寄存器文件的操作数,以产生操作数读取请求,并确保所选择的操作数中的两个或更多个不存储在多个存储区的同一个存储区中 银行寄存器文件。 由操作数读取请求指定的操作数在单个时钟周期内从多存储体寄存器文件读取。 然后由指令指定的操作数从多存储寄存器文件中读取并在一个或多个时钟周期内采集,执行每条指令。