公开(公告)号：US20060092750A1

公开(公告)日：2006-05-04

申请号：US11232170

申请日：2005-09-21

申请人： Byung-Gil Jeon ,  Byung-Jun Min ,  Kang-Woon Lee ,  Han-Joo Lee

发明人： Byung-Gil Jeon ,  Byung-Jun Min ,  Kang-Woon Lee ,  Han-Joo Lee

IPC分类号： G11C8/00

CPC分类号： G11C8/08 ,  G11C8/14

摘要： A semiconductor memory device having a word line driver circuit configured in stages. A plurality of sub word line driver circuits are connected, in parallel, to each main word line, and provide a sub word line enable signal to a selected sub word line in response to a main word line enable signal provided through a main word line. A plurality of (local) word line driver circuits are connected in parallel, to each sub word line and provide a local word line enable signal to a selected local word line in response to the (main/sub) word line enable signal so as to operate a plurality of memory cells connected to the selected local word line. The transistor count and layout area of a semiconductor memory device decreases and a reduced chip area can be achieved.

摘要翻译： 具有分级配置的字线驱动电路的半导体存储装置。 多个子字线驱动器电路并联连接到每个主字线，并且响应于通过主字线提供的主字线使能信号，向所选择的子字线提供子字线使能信号。 多个（本地）字线驱动电路并联连接到每个子字线，并且响应于（主/副）字线使能信号，向选定的本地字线提供本地字线使能信号，以便 操作连接到所选择的本地字线的多个存储器单元。 半导体存储器件的晶体管数量和布局面积减小，芯片面积减小。

公开(公告)号：US20100293323A1

公开(公告)日：2010-11-18

申请号：US12843135

申请日：2010-07-26

申请人： Byung-Gil Jeon ,  Kang-Woon Lee ,  Byung-Jun Min ,  Han-Joo Lee

发明人： Byung-Gil Jeon ,  Kang-Woon Lee ,  Byung-Jun Min ,  Han-Joo Lee

IPC分类号： G06F12/02

CPC分类号： G11C16/26 ,  G11C16/349

摘要： A flash memory device and a flash memory system are disclosed. The flash memory device includes a first non-volatile memory including a plurality of page data cells, storing page data, and reading and outputting the stored page data when a read command is applied from an external portion; and a second non-volatile memory including a plurality of spare data cells respectively adjacent to the plurality of page data cells, storing spare data, scanning the spare data and temporarily storing corresponding information when a file system is mounted, reading and outputting the stored spare data when the read command is applied.

摘要翻译： 公开了闪存设备和闪存系统。 闪速存储装置包括：第一非易失性存储器，包括多个页数据单元，存储页数据;以及当从外部部分施加读命令时，读出并输出存储的页数据; 以及第二非易失性存储器，其包括分别与所述多个页数据单元相邻的多个备用数据单元，存储备用数据，扫描备用数据并在安装文件系统时临时存储相应的信息，读取并输出所存储的备用 应用读命令时的数据。

公开(公告)号：US07477536B2

公开(公告)日：2009-01-13

申请号：US11602280

申请日：2006-11-21

申请人： Byung-Gil Jeon ,  Kang-Woon Lee ,  Byung-Jun Min ,  Han-Joo Lee

发明人： Byung-Gil Jeon ,  Kang-Woon Lee ,  Byung-Jun Min ,  Han-Joo Lee

IPC分类号： G11C11/34

CPC分类号： G11C11/22

摘要： A ferroelectric random access memory (FRAM) device includes a memory cell array including a plurality of FRAM cells connected to a first bit line and a reference cell connected to a second bit line. The device also includes a sense amplifier circuit configured to evaluate an amount of charges induced in a FRAM cell at a first mode and sense data stored in the FRAM cell at a second mode, wherein the sense amplifier circuit comprises a reference voltage generator configured to output an externally applied voltage as a reference voltage at the first mode, and output the reference voltage in response to a voltage applied to the second bit line from the reference cell and a voltage charged to an offset node at the second mode, and an amplifier circuit configured to sense and amplify a difference between a voltage applied to the first bit line from a selected FRAM cell and the reference voltage.

摘要翻译： 铁电随机存取存储器（FRAM）装置包括存储单元阵列，其包括连接到第一位线的多个FRAM单元和连接到第二位线的参考单元。 该装置还包括读出放大器电路，其被配置为评估在第一模式下在FRAM单元中感应的电荷量并且以第二模式感测存储在FRAM单元中的数据，其中读出放大器电路包括参考电压发生器，其被配置为输出 外部施加的电压作为第一模式的参考电压，并且响应于从参考单元施加到第二位线的电压和在第二模式下充电到偏移节点的电压输出参考电压，以及放大器电路 被配置为感测和放大从所选择的FRAM单元施加到第一位线的电压与参考电压之间的差。

公开(公告)号：US20080016306A1

公开(公告)日：2008-01-17

申请号：US11567844

申请日：2006-12-07

申请人： Byung-Jun Min ,  Kang-Woon Lee ,  Han-Joo Lee ,  Byung-Gil Jeon

发明人： Byung-Jun Min ,  Kang-Woon Lee ,  Han-Joo Lee ,  Byung-Gil Jeon

IPC分类号： G06F12/14 ,  G06F12/00

CPC分类号： G06F12/0638

摘要： A semiconductor memory having two different memory areas in one chip includes a memory cell array including a first variable memory area controlled to be accessible in at least first and second operation modes, and a second variable memory area controlled to be inaccessible in owe of the first and second operation modes; and a memory control unit for storing area information discriminating between the first memory area and the second memory area and generating memory control signals for controlling access to the first memory area and the second memory area. One memory can be substituted for a memory combination including ROMs and RAMs in one chip.

摘要翻译： 在一个芯片中具有两个不同存储区域的半导体存储器包括存储单元阵列，该存储单元阵列包括被控制为在至少第一和第二操作模式中可访问的第一可变存储区，以及被控制为不可访问的第一可变存储区， 和第二操作模式; 以及存储器控制单元，用于存储识别第一存储区域和第二存储区域之间的区域信息，并产生用于控制对第一存储区域和第二存储区域的访问的存储器控​​制信号。 一个存储器可以替代包括一个芯片中的ROM和RAM的存储器组合。

公开(公告)号：US20060126372A1

公开(公告)日：2006-06-15

申请号：US11301920

申请日：2005-12-13

申请人： Kang-Woon Lee ,  Byung-Jun Min ,  Han-Joo Lee ,  Byung-Gil Jeon

发明人： Kang-Woon Lee ,  Byung-Jun Min ,  Han-Joo Lee ,  Byung-Gil Jeon

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： A drive circuit of a FRAM (Ferroelectric Random Access Memory) includes an address buffer circuit that buffers an applied external address signal and generates an internal address signal, and detects a transition of the internal address signal and generates address transition detection signals for respective internal address signals. The FRAM includes a composite pulse signal generating circuit which limits a subsequent generation of a composite pulse signal for a delay interval provided after a generation of a previous composite pulse signal, in generating the second composite pulse signal obtained by totaling the respective address transition detection signals. The FRAM includes an internal chip enable buffer circuit which generates an internal chip enable signal to generate an internal control signal, in response to the composite pulse signal.

摘要翻译： FRAM（铁电随机存取存储器）的驱动电路包括缓存施加的外部地址信号并产生内部地址信号的地址缓冲器电路，并检测内部地址信号的转换，并产生各自内部地址的地址转换检测信号 信号。 FRAM包括复合脉冲信号发生电路，其在生成先前的复合脉冲信号之后，在产生通过对各个地址转换检测信号进行合并而获得的第二复合脉冲信号的同时限制复合脉冲信号的后续生成， 。 FRAM包括内部芯片使能缓冲电路，其响应于复合脉冲信号而产生内部芯片使能信号以产生内部控制信号。

公开(公告)号：US20060092725A1

公开(公告)日：2006-05-04

申请号：US11238198

申请日：2005-09-29

申请人： Byung-Jun Min ,  Kang-Woon Lee ,  Han-Joo Lee ,  Byung-Gil Jeon

发明人： Byung-Jun Min ,  Kang-Woon Lee ,  Han-Joo Lee ,  Byung-Gil Jeon

IPC分类号： G11C29/00

CPC分类号： G11C29/789 ,  G11C29/787

摘要： A redundancy circuit and repair method for a semiconductor memory device. The redundancy circuit comprises an address buffer for outputting a first internal address and a second internal address (used only during redundancy programming to carry failed memory addresses) based on an external address; and address storage and comparison units, each one of the address storage and comparison units being selected for programming using the second internal address. The address storage and comparison units comprise ferroelectric storage cells that store the address of a defective (failed) main memory cell and outputs a redundancy decoder enable signal in response to a first internal address matching the stored (second internal) address. Accordingly, the redundancy circuit with ferroelectric storage cells and a repair method allows the performance of a second repair when a defective cell is detected after a first repair or after a packaging process.

摘要翻译： 一种用于半导体存储器件的冗余电路和修复方法。 冗余电路包括用于基于外部地址输出第一内部地址和第二内部地址（仅在冗余编程中使用以携带失败的存储器地址）的地址缓冲器; 以及地址存储和比较单元，使用第二内部地址选择每个地址存储和比较单元进行编程。 地址存储和比较单元包括存储故障（故障）主存储单元的地址的铁电存储单元，并且响应于与存储的（第二内部）地址匹配的第一内部地址而输出冗余解码器使能信号。 因此，具有铁电存储单元的冗余电路和修复方法允许在第一修复或包装处理之后检测到缺陷单元时执行第二次修复。

公开(公告)号：US08300465B2

公开(公告)日：2012-10-30

申请号：US12843135

申请日：2010-07-26

申请人： Byung-Gil Jeon ,  Kang-Woon Lee ,  Byung-Jun Min ,  Han-Joo Lee

发明人： Byung-Gil Jeon ,  Kang-Woon Lee ,  Byung-Jun Min ,  Han-Joo Lee

IPC分类号： G11C16/04

CPC分类号： G11C16/26 ,  G11C16/349

摘要： A flash memory device and a flash memory system are disclosed. The flash memory device includes a first non-volatile memory including a plurality of page data cells, storing page data, and reading and outputting the stored page data when a read command is applied from an external portion; and a second non-volatile memory including a plurality of spare data cells respectively adjacent to the plurality of page data cells, storing spare data, scanning the spare data and temporarily storing corresponding information when a file system is mounted, reading and outputting the stored spare data when the read command is applied.

摘要翻译： 公开了闪存设备和闪存系统。 闪速存储装置包括：第一非易失性存储器，包括多个页数据单元，存储页数据;以及当从外部部分施加读命令时，读出并输出存储的页数据; 以及第二非易失性存储器，其包括分别与所述多个页数据单元相邻的多个备用数据单元，存储备用数据，扫描备用数据并在安装文件系统时临时存储相应的信息，读取并输出所存储的备用 应用读命令时的数据。

公开(公告)号：US07787297B2

公开(公告)日：2010-08-31

申请号：US12040282

申请日：2008-02-29

申请人： Byung-Gil Jeon ,  Kang-Woon Lee ,  Byung-Jun Min ,  Han-Joo Lee

发明人： Byung-Gil Jeon ,  Kang-Woon Lee ,  Byung-Jun Min ,  Han-Joo Lee

IPC分类号： G11C16/04

CPC分类号： G11C16/26 ,  G11C16/349

摘要： A flash memory device and a flash memory system are disclosed. The flash memory device includes a first non-volatile memory including a plurality of page data cells, storing page data, and reading and outputting the stored page data when a read command is applied from an external portion; and a second non-volatile memory including a plurality of spare data cells respectively adjacent to the plurality of page data cells, storing spare data, scanning the spare data and temporarily storing corresponding information when a file system is mounted, reading and outputting the stored spare data when the read command is applied.

摘要翻译： 公开了闪存设备和闪存系统。 闪速存储装置包括：第一非易失性存储器，包括多个页数据单元，存储页数据;以及当从外部部分施加读命令时，读出并输出存储的页数据; 以及第二非易失性存储器，其包括分别与所述多个页数据单元相邻的多个备用数据单元，存储备用数据，扫描备用数据并在安装文件系统时临时存储相应的信息，读取并输出所存储的备用 应用读命令时的数据。

公开(公告)号：US07616514B2

公开(公告)日：2009-11-10

申请号：US11212311

申请日：2005-08-26

申请人： Kang-Woon Lee ,  Byung Jun Min ,  Han-Joo Lee ,  Byung-Gil Jeon

发明人： Kang-Woon Lee ,  Byung Jun Min ,  Han-Joo Lee ,  Byung-Gil Jeon

IPC分类号： G11C7/14 ,  G11C7/02

CPC分类号： G11C11/22 ,  G11C7/06 ,  G11C7/14 ,  G11C2207/2227

摘要： A reference voltage supply apparatus and a driving method thereof in a ferroelectric memory device provide a reference voltage stabilized against the imprint effect thus maintaining reading reliability of the device. In the reference voltage supply apparatus (e.g., using a non-switching capacitance of a ferroelectric capacitor), a reference cell is constructed of a ferroelectric capacitor and an access switch, and provides a reference voltage to read data from a memory cell. In an active mode, the reference cell stores data of a first logic state (e.g., corresponding to the non-switching capacitance of the ferroelectric capacitor), in the reference cell, and then supplies, as a reference voltage, the voltage corresponding to the data of the first logic state to a bit line; and in a stand-by mode, a reference voltage controller stores (writes) data of a second logic state (opposite to the first logic state), into the reference cell.

摘要翻译： 铁电存储器件中的参考电压提供装置及其驱动方法提供了抵抗印记效应的稳定的参考电压，从而保持了器件的读取可靠性。 在参考电压供给装置（例如，使用铁电电容器的非开关电容）中，参考单元由铁电电容器和存取开关构成，并且提供参考电压以从存储单元读取数据。 在活动模式中，参考单元存储参考单元中的第一逻辑状态（例如，对应于铁电电容器的非开关电容）的数据，然后将对应于 第一逻辑状态的数据到位线; 并且在待机模式中，参考电压控制器将第二逻辑状态（与第一逻辑状态相反）的数据存储（写入）到参考单元中。

公开(公告)号：US20080266962A1

公开(公告)日：2008-10-30

申请号：US12040282

申请日：2008-02-29

申请人： Byung-Gil Jeon ,  Kang-Woon Lee ,  Byung-Jun Min ,  Han-Joo Lee

发明人： Byung-Gil Jeon ,  Kang-Woon Lee ,  Byung-Jun Min ,  Han-Joo Lee

IPC分类号： G11C16/06

CPC分类号： G11C16/26 ,  G11C16/349

摘要： A flash memory device and a flash memory system are disclosed. The flash memory device includes a first non-volatile memory including a plurality of page data cells, storing page data, and reading and outputting the stored page data when a read command is applied from an external portion; and a second non-volatile memory including a plurality of spare data cells respectively adjacent to the plurality of page data cells, storing spare data, scanning the spare data and temporarily storing corresponding information when a file system is mounted, reading and outputting the stored spare data when the read command is applied.

摘要翻译： 公开了闪存设备和闪存系统。 闪速存储装置包括：第一非易失性存储器，包括多个页数据单元，存储页数据;以及当从外部部分施加读命令时，读出并输出存储的页数据; 以及第二非易失性存储器，其包括分别与所述多个页数据单元相邻的多个备用数据单元，存储备用数据，扫描备用数据并在安装文件系统时临时存储相应的信息，读取并输出所存储的备用 应用读命令时的数据。