公开(公告)号：US09343052B2

公开(公告)日：2016-05-17

申请号：US14661410

申请日：2015-03-18

Applicant: CASIO COMPUTER CO., LTD.

Inventor： Goro Sakata

IPC: G10H1/06 ,  G10H1/34 ,  H03M3/00 ,  G10H7/00

CPC classification number: G10H1/34 ,  G10H7/002 ,  G10H2240/071 ,  G10H2250/545 ,  H03M3/388 ,  H03M3/506

Abstract: In the present embodiment, quantizer output values including variation values corresponding to duty errors of pulse width data (PWM output signals) occurring by the difference of the pull-down/pull-up drive characteristics (drive capabilities) of a buffer are stored in advance in a feedback value memory in a quantizer as feedback values FBV0 to FBV4, and a feedback value FBVn read out from the feedback value memory in response to the quantization of a delta-sigma modulation output is inputted into a subtractor by return input. Then, a quantizer output value including a variation value corresponding to a duty error is subtracted from input data Din, and delta-sigma modulation is performed such that the difference is minimized, whereby the duty error of pulse width data (PWM output signal) is compensated.

Abstract translation: 在本实施例中，预先存储包括由缓冲器的下拉/上拉驱动特性（驱动能力）的差引起的脉冲宽度数据（PWM输出信号）的占空比误差对应的量化器输出值 在量化器中的反馈值存储器中作为反馈值FBV0至FBV4，并且响应于Δ-Σ调制输出的量化从反馈值存储器读出的反馈值FBVn通过返回输入被输入减法器。 然后，从输入数据Din中减去包括与占空比误差对应的变化值的量化器输出值，进行Δ-Σ调制使差值最小化，由此脉冲宽度数据（PWM输出信号）的占空误差为 补偿。

公开(公告)号：US09029679B2

公开(公告)日：2015-05-12

申请号：US14467286

申请日：2014-08-25

Applicant: Casio Computer Co., Ltd.

Inventor： Goro Sakata ,  Akira Ikeda

IPC: G10H3/00 ,  G10H1/34 ,  G10H1/02

CPC classification number: G10H1/34 ,  G10H2220/285 ,  G10H2220/295

Abstract: In a touch detection apparatus 50, the controller 51 predicts damper-on arrival time as time of arrival of generation of a damper-on event based on a period of time counted by a first counter 54 from when a second contact point 160b is turned off until when a first contact point 160a is turned off. The second counter 55 counts time to be compared to the damper-on arrival time. The comparator circuit 58 compares the time counted by the second counter 55 and the damper-on arrival time. If the time counted by the second counter 55 and the damper-on arrival time agree with each other, the comparator circuit 58 transmits a key release agreement signal triggering generation of a damper-on event to the controller 51. If the key release agreement signal is transmitted from the comparator circuit 58, the controller 51 executes control to generate a damper-on event.

Abstract translation: 在触摸检测装置50中，控制器51基于从第一计数器54计数的时间从第二接触点160b关闭的时间段预测作为阻尼器接通事件的产生的到达时间的阻尼器到达时间 直到第一接触点160a关闭。 第二计数器55计算要与阻尼器到达时间进行比较的时间。 比较器电路58比较由第二计数器55计数的时间和阻尼器到达时间。 如果由第二计数器55计算的时间和阻尼器到达时间彼此一致，则比较器电路58向控制器51发送触发产生阻尼器开启事件的密钥释放协议信号。如果密钥释放协议信号 从比较器电路58发送，控制器51执行控制以产生阻尼器接通事件。

公开(公告)号：US11764803B2

公开(公告)日：2023-09-19

申请号：US17706012

申请日：2022-03-28

Applicant: CASIO COMPUTER CO., LTD.

Inventor： Goro Sakata

IPC: H03M3/00 ,  G10H1/34 ,  G10H7/08

CPC classification number: H03M3/506 ,  G10H1/344 ,  G10H7/08 ,  H03M3/42

Abstract: A digital-to-analog conversion device which performs integration processing for integrating a difference between an input signal and a first return signal generated based on the input signal, and outputting an integration result, first quantization processing for quantizing the integration result, and outputting a first quantization signal, first return signal output processing for outputting the first return signal by adding to the first quantization signal a correction value delay signal acquired by a correction value signal outputted based on the integration result being delayed, and output processing for outputting output signals including a signal whose pulse width is asymmetrical to center of a processing period, based on the first quantization signal, in which the correction value signal includes a signal indicating a correction value for correcting a difference between a center of the pulse width asymmetrical to the center of the processing period and the center of the processing period.

公开(公告)号：US11316529B2

公开(公告)日：2022-04-26

申请号：US16477504

申请日：2018-01-16

Applicant: CASIO COMPUTER CO., LTD.

Inventor： Goro Sakata

IPC: H03M3/00 ,  G10H1/34 ,  G10H7/08

Abstract: A digital-to-analog conversion device which performs integration processing for integrating a difference between an input signal and a first return signal generated based on the input signal, and outputting an integration result, first quantization processing for quantizing the integration result, and outputting a first quantization signal, first return signal output processing for outputting the first return signal by adding to the first quantization signal a correction value delay signal acquired by a correction value signal outputted based on the integration result being delayed, and output processing for outputting output signals including a signal whose pulse width is asymmetrical to center of a processing period, based on the first quantization signal, in which the correction value signal includes a signal indicating a correction value for correcting a difference between a center of the pulse width asymmetrical to the center of the processing period and the center of the processing period.

公开(公告)号：US11094307B2

公开(公告)日：2021-08-17

申请号：US16591588

申请日：2019-10-02

Applicant: CASIO COMPUTER CO., LTD.

Inventor： Goro Sakata

IPC: G10H1/14 ,  G10H1/00 ,  G10H1/34 ,  G10H7/00

Abstract: An electronic musical instrument includes a playing operator, and a sound source which performs processing of receiving, in response to a user operation on the playing operator, a sound generation instruction according to playing operation information including the pitch information indicating the certain pitch and sound volume information indicating a certain volume, and generating sound according to the certain pitch and the certain volume, based on excitation data generated by multiplying partial data by a window function, the partial data being included in excitation signal waveform data generated based on a plurality of waveform data items which are respectively different from each other in sound intensity in the certain pitch.

公开(公告)号：US10515618B2

公开(公告)日：2019-12-24

申请号：US16239073

申请日：2019-01-03

Applicant: CASIO COMPUTER CO., LTD.

Inventor： Goro Sakata

IPC: G10H7/04 ,  G10H7/00 ,  G06F16/61 ,  G11B20/12 ,  G10H1/00 ,  G10H7/02 ,  G10L19/16

Abstract: A waveform data structure includes a plurality of types of frames having different data sizes. Each of the plurality of types of frames includes an auxiliary information area and a data area. The auxiliary information area includes an area for storing common effective-bit length data for a section of waveform samples, and an area for storing an identifier for identifying one of the plurality of types of frames. The data area is an area for storing extracted waveform samples which are extracted from the waveform samples based on the common effective-bit length. The number of the extracted waveform samples is determined based on the common effective-bit length.

公开(公告)号：US10249279B1

公开(公告)日：2019-04-02

申请号：US16124609

申请日：2018-09-07

Applicant: CASIO COMPUTER CO., LTD.

Inventor： Goro Sakata

IPC: G10H5/00 ,  H03M3/00 ,  H03F3/181

Abstract: A digital-to-analog converter performs a ΔΣ computation process to start the ΔΣ computation based upon the second clock signal with respect to the digital data of music sound if the ΔΣ computation is not under execution when the control signal is outputted by the signal output process, a control process to inhibit the ΔΣ computation based upon the second clock signal from being started with respect to the digital data of music sound until the ΔΣ computation is not under execution when the ΔΣ computation is under execution, and an output process to convert a computation result of the ΔΣ computation process into an analog signal and output the analog signal.