公开(公告)号：US20120081980A1

公开(公告)日：2012-04-05

申请号：US12897078

申请日：2010-10-04

Applicant: Chun-Yu Chiu

Inventor： Chun-Yu Chiu

IPC: G11C7/00

CPC classification number: G11C11/413 ,  G11C7/227

Abstract: A memory including a memory cell array, a word line decoder, a first and a second reference bit line generators are provided. The memory cell array has first and last bit lines respectively disposed at two sides of the memory cell array. The word line decoder generates a pre-word line signal. The first and the second reference bit line generators respectively detect voltage level variations of the first and last bit lines according to the pre-word line signal, so as to generate a first and a second cut-back signals. The first reference bit line generator transmits the first cut-back signal to the second reference bit line generator, the second reference bit line generator transmits the first and the second cut-back signals to the word line decoder, and the word line decoder generates a word line signal according to the first and the second cut-back signals and the pre-word line signal.

Abstract translation: 提供了包括存储单元阵列，字线解码器，第一和第二参考位线发生器的存储器。 存储单元阵列具有分别设置在存储单元阵列的两侧的第一和最后位线。 字线解码器产生预字线信号。 第一和第二参考位线发生器分别根据预字线信号检测第一和最后位线的电压电平变化，以产生第一和第二切断信号。 第一参考位线发生器将第一切断信号发送到第二参考位线发生器，第二参考位线发生器将第一和第二切断信号发送到字线解码器，并且字线解码器产生 根据第一和第二切断信号和预字线信号的字线信号。

公开(公告)号：US08013648B1

公开(公告)日：2011-09-06

申请号：US12835166

申请日：2010-07-13

Applicant: Lieh-Chiu Lin ,  Chun-Yu Chiu

Inventor： Lieh-Chiu Lin ,  Chun-Yu Chiu

IPC: H03K5/12

CPC classification number: H03K5/04 ,  H03K19/00361 ,  H04L25/026

Abstract: An output slew-rate controlled interface is provided. The output slew-rate controlled interface includes: a standard slew-rate range generating circuit, for generating at least one standard signal defining a standard slew-rate range; a slew-rate comparing circuit, coupled to the standard slew-rate range generating circuit and a load circuit coupled to the interface, for comparing a response slew-rate of a response signal from the load circuit with the standard slew-rate range and producing a comparison result; and an outputting circuit, coupled to the slew-rate comparing circuit, for adjusting an output slew-rate of an output signal according to the comparison result and outputting the output signal to the load circuit.

Abstract translation: 提供输出转换速率控制接口。 输出转换速率控制接口包括：标准转换速率范围发生电路，用于产生定义标准转换速率范围的至少一个标准信号; 耦合到标准压摆率范围产生电路的转换速率比较电路和耦合到该接口的负载电路，用于将来自负载电路的响应信号的响应转换速率与标准转换速率范围进行比较，并产生 比较结果; 以及输出电路，其耦合到所述转换速率比较电路，用于根据所述比较结果调整输出信号的输出转换速率，并将所述输出信号输出到所述负载电路。

公开(公告)号：US20100228910A1

公开(公告)日：2010-09-09

申请号：US12397269

申请日：2009-03-03

Applicant: Chun-Yu Chiu

Inventor： Chun-Yu Chiu

IPC: G06F12/06

CPC classification number: G06F13/1626 ,  Y02D10/14

Abstract: A system and method for resolving request collision in a single-port static random access memory (SRAM) are disclosed. A first SRAM part and a second SRAM part of the single-port SRAM are accessed in turn. When request collision occurs, data is temporarily stored in a first or second shadow bank associated with the first or the second SRAM part which is under access. The temporarily stored data is then transferred, at a later time, to an associated one of the first/second SRAM parts while the other one of the first/second SRAM parts is being accessed.

Abstract translation: 公开了一种用于解决单端口静态随机存取存储器（SRAM）中的请求冲突的系统和方法。 依次访问单端口SRAM的第一个SRAM部分和第二个SRAM部分。 当发生请求冲突时，数据被临时存储在与正在访问的第一或第二SRAM部分相关联的第一或第二影子库中。 然后，临时存储的数据在稍后的时间被传送到第一/第二SRAM部分中的相关联的一个，而第一/第二SRAM部分中的另一个被访问。