公开(公告)号：US08013648B1

公开(公告)日：2011-09-06

申请号：US12835166

申请日：2010-07-13

Applicant: Lieh-Chiu Lin ,  Chun-Yu Chiu

Inventor： Lieh-Chiu Lin ,  Chun-Yu Chiu

IPC: H03K5/12

CPC classification number: H03K5/04 ,  H03K19/00361 ,  H04L25/026

Abstract: An output slew-rate controlled interface is provided. The output slew-rate controlled interface includes: a standard slew-rate range generating circuit, for generating at least one standard signal defining a standard slew-rate range; a slew-rate comparing circuit, coupled to the standard slew-rate range generating circuit and a load circuit coupled to the interface, for comparing a response slew-rate of a response signal from the load circuit with the standard slew-rate range and producing a comparison result; and an outputting circuit, coupled to the slew-rate comparing circuit, for adjusting an output slew-rate of an output signal according to the comparison result and outputting the output signal to the load circuit.

Abstract translation: 提供输出转换速率控制接口。 输出转换速率控制接口包括：标准转换速率范围发生电路，用于产生定义标准转换速率范围的至少一个标准信号; 耦合到标准压摆率范围产生电路的转换速率比较电路和耦合到该接口的负载电路，用于将来自负载电路的响应信号的响应转换速率与标准转换速率范围进行比较，并产生 比较结果; 以及输出电路，其耦合到所述转换速率比较电路，用于根据所述比较结果调整输出信号的输出转换速率，并将所述输出信号输出到所述负载电路。

公开(公告)号：US07885109B2

公开(公告)日：2011-02-08

申请号：US12273414

申请日：2008-11-18

Applicant: Wen-Pin Lin ,  Shyh-Shyuan Sheu ,  Lieh-Chiu Lin ,  Pei-Chia Chiang

Inventor： Wen-Pin Lin ,  Shyh-Shyuan Sheu ,  Lieh-Chiu Lin ,  Pei-Chia Chiang

IPC: G11C11/04

CPC classification number: G11C8/08 ,  G11C11/4085 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0028 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2013/0078 ,  G11C2207/2227 ,  G11C2213/79

Abstract: Memories with low power consumption and methods for suppressing current leakage of a memory. The memory cell of the memory has a storage element and a transistor coupled in series. The invention sets a voltage across the transistor approaching to zero when the memory is not been accessed.

Abstract translation: 具有低功耗的存储器和用于抑制存储器的电流泄漏的方法。 存储器的存储单元具有串联耦合的存储元件和晶体管。 当存储器未被访问时，本发明将跨越晶体管的电压设置为零。

公开(公告)号：US20080310217A1

公开(公告)日：2008-12-18

申请号：US11948486

申请日：2007-11-30

Applicant: Pei-Chia Chiang ,  Shyh-Shyuan Sheu ,  Lieh-Chiu Lin

Inventor： Pei-Chia Chiang ,  Shyh-Shyuan Sheu ,  Lieh-Chiu Lin

IPC: G11C11/00 ,  G11C7/00

CPC classification number: G11C5/147 ,  G11C13/0004 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2013/0078

Abstract: A writing circuit for a phase change memory is provided. The writing circuit comprises a driving current generating circuit, a first switch device, a first memory cell and a second switch device. The driving current generating circuit provides a writing current to the first memory cell. The first switch device is coupled to the driving current generating circuit. The first memory cell is coupled between the first switch device and the second switch device. The second switch device is coupled between the first memory cell and a ground, wherein when the driving current generating circuit outputs the writing current to the first memory cell, the second switch device is turned on after the first switch device has been turned on for a first predetermined time period.

Abstract translation: 提供了一种用于相变存储器的写入电路。 写入电路包括驱动电流产生电路，第一开关器件，第一存储器单元和第二开关器件。 驱动电流产生电路向第一存储单元提供写入电流。 第一开关器件耦合到驱动电流产生电路。 第一存储器单元耦合在第一开关器件和第二开关器件之间。 第二开关装置耦合在第一存储单元和地之间，其中当驱动电流产生电路向第一存储单元输出写入电流时，第二开关器件在第一开关器件接通之后导通， 第一预定时间段。

公开(公告)号：US20080239798A1

公开(公告)日：2008-10-02

申请号：US12000981

申请日：2007-12-19

Applicant: Shyh-Shyuan Sheu ,  Lieh-Chiu Lin ,  Pei-Chia Chiang

Inventor： Shyh-Shyuan Sheu ,  Lieh-Chiu Lin ,  Pei-Chia Chiang

IPC: G11C11/00 ,  G11C7/00

CPC classification number: G11C7/1078 ,  G11C7/1096 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0078

Abstract: One embodiment of the invention provides a compensation circuit. The compensation circuit comprises a writing driver, a distance detection circuit, an operating element and an auxiliary writing driver. The writing driver provides a writing current to a writing path. The distance detection circuit is coupled to the writing path to detect a distance that the writing current has travelled and outputs a control signal based on the distance. The operating element is coupled to the writing path. The auxiliary writing driver provides an auxiliary current to the writing path based on the control signal.

Abstract translation: 本发明的一个实施例提供一种补偿电路。 补偿电路包括写入驱动器，距离检测电路，操作元件和辅助写入驱动器。 写入驱动器向写入路径提供写入电流。 距离检测电路耦合到写入路径以检测写入电流已经行进的距离，并且基于该距离输出控制信号。 操作元件耦合到写入路径。 辅助写入驱动器基于控制信号向写入路径提供辅助电流。

公开(公告)号：USRE45189E1

公开(公告)日：2014-10-14

申请号：US13571798

申请日：2012-08-10

Applicant: Shyh-Shyuan Sheu ,  Lieh-Chiu Lin ,  Pei-Chia Chiang ,  Wen-Pin Lin

Inventor： Shyh-Shyuan Sheu ,  Lieh-Chiu Lin ,  Pei-Chia Chiang ,  Wen-Pin Lin

IPC: G11C11/00

CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C13/0064

Abstract: An embodiment of a writing system for a phase change memory based on a present application is disclosed. The writing system comprises a first phase change memory (PCM) cell, a second PCM cell, a first writing circuit and a verifying circuit. The first writing circuit executes a writing procedure, receives and writes a first data to the first PCM cell. The verifying circuit executes a verifying procedure and the circuit further comprises a processing unit and a second writing circuit. The processing unit reads and compares the data stored in the second PCM cell with a second data. The second writing circuit writes the second data to the second PCM cell when the data stored in the second PCM cell and the second data are not matched.

Abstract translation: 公开了一种基于本申请的相变存储器的写入系统的实施例。 该写入系统包括第一相变存储器（PCM）单元，第二PCM单元，第一写入电路和验证电路。 第一写入电路执行写入过程，将第一数据接收并写入第一PCM单元。 验证电路执行验证过程，并且电路还包括处理单元和第二写入电路。 处理单元读取并比较存储在第二PCM单元中的数据与第二数据。 当存储在第二PCM单元中的数据和第二数据不匹配时，第二写入电路将第二数据写入第二PCM单元。

公开(公告)号：US08031515B2

公开(公告)日：2011-10-04

申请号：US12275223

申请日：2008-11-21

Applicant: Shyh-Shyuan Sheu ,  Lieh-Chiu Lin ,  Pei-Chia Chiang ,  Wen-Pin Lin

Inventor： Shyh-Shyuan Sheu ,  Lieh-Chiu Lin ,  Pei-Chia Chiang ,  Wen-Pin Lin

IPC: G11C11/00

CPC classification number: G11C11/5678 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2013/0092

Abstract: A data programming circuit for storing a writing data into a memory cell is provided. The data programming circuit includes a control circuit and a current generating circuit. The control circuit generates a control signal according to the writing data. The current generating circuit provides a writing current to the memory cell to change a crystalline state of the memory cell. The writing current has a pulse width corresponding to the writing data, and the crystalline state corresponds to the writing data.

Abstract translation: 提供了一种用于将写入数据存储到存储单元中的数据编程电路。 数据编程电路包括控制电路和电流产生电路。 控制电路根据写入数据生成控制信号。 电流产生电路向存储单元提供写入电流以改变存储单元的结晶状态。 写入电流具有对应于写入数据的脉冲宽度，并且结晶状态对应于写入数据。

公开(公告)号：US20090135645A1

公开(公告)日：2009-05-28

申请号：US12275223

申请日：2008-11-21

Applicant: Shyh-Shyuan Sheu ,  Lieh-Chiu Lin ,  Pei-Chia Chiang ,  Wen-Pin Lin

Inventor： Shyh-Shyuan Sheu ,  Lieh-Chiu Lin ,  Pei-Chia Chiang ,  Wen-Pin Lin

IPC: G11C7/00 ,  G11C11/56

CPC classification number: G11C11/5678 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2013/0092

Abstract: A data programming circuit for storing a writing data into a memory cell is provided. The data programming circuit includes a control circuit and a current generating circuit. The control circuit generates a control signal according to the writing data. The current generating circuit provides a writing current to the memory cell to change a crystalline state of the memory cell. The writing current has a pulse width corresponding to the writing data, and the crystalline state corresponds to the writing data.

Abstract translation: 提供了一种用于将写入数据存储到存储单元中的数据编程电路。 数据编程电路包括控制电路和电流产生电路。 控制电路根据写入数据生成控制信号。 电流产生电路向存储单元提供写入电流以改变存储单元的结晶状态。 写入电流具有对应于写入数据的脉冲宽度，并且结晶状态对应于写入数据。

公开(公告)号：US20090080243A1

公开(公告)日：2009-03-26

申请号：US12142724

申请日：2008-06-19

Applicant: Pei-Chia Chiang ,  Shyh-Shyuan Sheu ,  Lieh-Chiu Lin ,  Wen-Pin Lin

Inventor： Pei-Chia Chiang ,  Shyh-Shyuan Sheu ,  Lieh-Chiu Lin ,  Wen-Pin Lin

IPC: G11C11/00

CPC classification number: G11C5/14 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2013/0078

Abstract: Devices controlling a phase change storage element and methods for increasing reliability of a phase change storage element. The invention introduces a first operation mode and a second operation mode. A reference phase change storage element is forced a write current for an ideal conduction period in the first operation mode. In the second operation mode, the invention generates a proper conduction period based on the resistance of the reference phase change storage element, and forces the write current into the controlled phase change storage element for the proper conduction period.

Abstract translation: 控制相变存储元件的装置和增加相变存储元件的可靠性的方法。 本发明引入了第一操作模式和第二操作模式。 参考相变存储元件在第一操作模式中强制写入电流以达到理想的导通时段。 在第二操作模式中，本发明基于参考相变存储元件的电阻产生适当的导通周期，并将写入电流强制到受控相变存储元件中以达到适当的导通周期。

公开(公告)号：US20090010047A1

公开(公告)日：2009-01-08

申请号：US11957044

申请日：2007-12-14

Applicant: Shyh-Shyuan Sheu ,  Lieh-Chiu Lin ,  Pei-Chia Chiang

Inventor： Shyh-Shyuan Sheu ,  Lieh-Chiu Lin ,  Pei-Chia Chiang

IPC: G11C11/56

CPC classification number: G11C13/0061 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2013/0092

Abstract: A phase change memory writing circuit is provided. The circuit comprises a writing path and a fast write control unit. The writing path further comprises a current driving unit, a first switch device and a phase change memory cell. The current driving unit is coupled to a high voltage source and outputs a driving current. The first switch device is controlled by a first control signal. The fast write control unit is coupled to the writing path to provide a writing voltage to the writing path. When the first switch device is turned off, the fast write control unit outputs the writing voltage to the writing path. When the first switch device is turned on, the fast write control unit stops outputting the writing voltage to the writing path.

Abstract translation: 提供了相变存储器写入电路。 该电路包括写入路径和快速写入控制单元。 写入路径还包括电流驱动单元，第一开关器件和相变存储器单元。 电流驱动单元耦合到高电压源并输出驱动电流。 第一开关装置由第一控制信号控制。 快速写入控制单元耦合到写入路径以向写入路径提供写入电压。 当第一开关装置关闭时，快速写入控制单元将写入电压输出到写入路径。 当第一开关装置接通时，快速写入控制单元停止向写入路径输出写入电压。

公开(公告)号：US07933147B2

公开(公告)日：2011-04-26

申请号：US11968041

申请日：2007-12-31

Applicant: Lieh-Chiu Lin ,  Shyh-Shyuan Sheu ,  Pei-Chia Chiang

Inventor： Lieh-Chiu Lin ,  Shyh-Shyuan Sheu ,  Pei-Chia Chiang

IPC: G11C11/00

CPC classification number: G11C7/08 ,  G11C7/12 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/004 ,  G11C2013/0054

Abstract: A sensing circuit of a phase change memory. The sensing circuit comprises a data current source and a reference current source, a storage memory device and a reference memory device, a storage switch and a reference switch, an auxiliary current source and a comparator. First terminals of the storage memory device and the reference memory device are respectively coupled to the data current source and the reference current source. The storage switch and the reference switch are respectively coupled to second terminals of the storage memory device and the reference memory device. The auxiliary current source is dynamically coupled to the first terminals of the storage memory device and the reference memory device. The comparator is coupled to the first terminals of the storage memory device and the reference memory device.

Abstract translation: 相变存储器的感测电路。 感测电路包括数据电流源和参考电流源，存储存储器件和参考存储器件，存储开关和参考开关，辅助电流源和比较器。 存储存储器件和参考存储器件的第一端子分别耦合到数据电流源和参考电流源。 存储开关和参考开关分别耦合到存储存储器件和参考存储器件的第二端子。 辅助电流源动态地耦合到存储存储器件和参考存储器件的第一端子。 比较器耦合到存储存储器件和参考存储器件的第一端子。