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公开(公告)号：US20160044412A1
公开(公告)日：2016-02-11
申请号：US14826891
申请日：2015-08-14
Inventor： Graeme Gordon Mackay , Jonathan Timothy Wigner , Gordon Richard McLeod
CPC classification number: H04R3/005 , H04B1/00 , H04B3/00 , H04H60/04 , H04R3/00 , H04R5/02 , H04R25/43 , H04R2420/01
Abstract: An integrated circuit for digital signal routing. The integrated circuit has analog and digital inputs and outputs, including digital interfaces for connection to other integrated circuits. Inputs, including the digital interfaces, act as data sources. Outputs, including the digital interfaces, act as data destinations. The integrated circuit also includes signal processing blocks, which can act as data sources and data destinations. Signal routing is achieved by means of a multiply-accumulate block, which takes data from one or more data source and, after any required scaling, generates output data for a data destination. Data from a data source is buffered for an entire period of a data sample clock so that the multiply-accumulate block can retrieve the data at any point in the period, and output data of the multiply-accumulate block is buffered for an entire period of the data sample clock so that the data destination can retrieve the data at any point in the period. Multiple signal paths can be defined by configuration data supplied to the device, either by a user, or by software. The multiply-accumulate block operates on a time division multiplexed basis, so that multiple signal paths can be processed within one period of the sample clock. Each signal path has a respective sample clock rate, and paths with different sample clock rates can be routed through the multiply-accumulate block on a time division multiplexed basis independently of each other. Thus, speech signals at 8 kHz or 16 kHz can be processed concurrently with audio data at 44.ikHz or 48 kHz.
Abstract translation: 一种用于数字信号路由的集成电路。 集成电路具有模拟和数字输入和输出，包括用于连接到其他集成电路的数字接口。 输入，包括数字接口，作为数据源。 输出，包括数字接口，充当数据目的地。 该集成电路还包括可用作数据源和数据目的地的信号处理块。 信号路由通过乘法累加块实现，该乘法块从一个或多个数据源获取数据，并且在任何所需的缩放之后生成数据目的地的输出数据。 来自数据源的数据在数据采样时钟的整个周期中被缓冲，使得乘法累加块可以在该周期中的任何点检索数据，并且乘法累加块的输出数据被缓冲在整个周期 数据采样时钟，使得数据目的地可以在该周期的任何时间点检索数据。 多个信号路径可以由用户或软件提供给设备的配置数据来定义。 乘法累加块以时分复用为基础进行操作，从而可以在采样时钟的一个周期内处理多个信号路径。 每个信号路径具有各自的采样时钟速率，并且具有不同采样时钟速率的路径可以彼此独立地以时分复用为基础通过乘法累加块路由。 因此，可以以44Hz或48kHz的音频数据同时处理8kHz或16kHz的语音信号。
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Patent Agency Ranking
公开(公告)号：US20210185440A1
公开(公告)日：2021-06-17
申请号：US17187897
申请日：2021-03-01
Inventor： Graeme Gordon Mackay , Jonathan Timothy Wigner , Gordon Richard McLeod
Abstract: An integrated circuit for digital signal routing. The integrated circuit has analog and digital inputs and outputs, including digital interfaces for connection to other integrated circuits. Inputs, including the digital interfaces, act as data sources. Outputs, including the digital interfaces, act as data destinations. The integrated circuit also includes signal processing blocks, which can act as data sources and data destinations. Signal routing is achieved by means of a multiply-accumulate block, which takes data from one or more data source and, after any required scaling, generates output data for a data destination. Data from a data source is buffered for an entire period of a data sample clock so that the multiply-accumulate block can retrieve the data at any point in the period, and output data of the multiply-accumulate block is buffered for an entire period of the data sample clock so that the data destination can retrieve the data at any point in the period. Multiple signal paths can be defined by configuration data supplied to the device, either by a user, or by software. The multiply-accumulate block operates on a time division multiplexed basis, so that multiple signal paths can be processed within one period of the sample clock. Each signal path has a respective sample clock rate, and paths with different sample clock rates can be routed through the multiply-accumulate block on a time division multiplexed basis independently of each other. Thus, speech signals at 8 kHz or 16 kHz can be processed concurrently with audio data at 44 .ikHz or 48 kHz.
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公开(公告)号：US20200296509A1
公开(公告)日：2020-09-17
申请号：US16885538
申请日：2020-05-28
Inventor： Graeme G. Mackay , Jonathan Timothy Wigner , Gordon Richard McLeod
Abstract: An integrated circuit for digital signal routing. The integrated circuit has analog and digital inputs and outputs, including digital interfaces for connection to other integrated circuits. Inputs, including the digital interfaces, act as data sources. Outputs, including the digital interfaces, act as data destinations. The integrated circuit also includes signal processing blocks, which can act as data sources and data destinations. Signal routing is achieved by means of a multiply-accumulate block, which takes data from one or more data source and, after any required scaling, generates output data for a data destination. Data from a data source is buffered for an entire period of a data sample clock so that the multiply-accumulate block can retrieve the data at any point in the period, and output data of the multiply-accumulate block is buffered for an entire period of the data sample clock so that the data destination can retrieve the data at any point in the period. Multiple signal paths can be defined by configuration data supplied to the device, either by a user, or by software. The multiply-accumulate block operates on a time division multiplexed basis, so that multiple signal paths can be processed within one period of the sample clock. Each signal path has a respective sample clock rate, and paths with different sample clock rates can be routed through the multiply-accumulate block on a time division multiplexed basis independently of each other. Thus, speech signals at 8 kHz or 16 kHz can be processed concurrently with audio data at 44.ikHz or 48 kHz.
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公开(公告)号：US10720171B1
公开(公告)日：2020-07-21
申请号：US16280288
申请日：2019-02-20
Inventor： John Paul Lesso , Gordon Richard McLeod
IPC: G06F17/00 , G10L19/16 , G10L19/005 , G10L21/038
Abstract: In a method of audio processing, a plurality of audio samples are received, and are concatenated to form a composite audio signal. The composite audio signal is analysed to identify audio artefacts associated with concatenation in the composite audio signal, and any identified audio artefacts are compensated for, to form a corrected composite audio signal. The corrected composite audio signal is provided to a voice biometrics module.
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公开(公告)号：US10540978B2
公开(公告)日：2020-01-21
申请号：US15992562
申请日：2018-05-30
Inventor： John Paul Lesso , Gordon Richard McLeod
Abstract: A method of speaker verification comprises: comparing a test input against a model of a user's speech obtained during a process of enrolling the user; obtaining a first score from comparing the test input against the model of the user's speech; comparing the test input against a first plurality of models of speech obtained from a first plurality of other speakers respectively; obtaining a plurality of cohort scores from comparing the test input against the plurality of models of speech obtained from a plurality of other speakers; obtaining statistics describing the plurality of cohort scores; modifying said statistics to obtain adjusted statistics; normalising the first score using the adjusted statistics to obtain a normalised score; and using the normalised score for speaker verification.
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公开(公告)号：US10212513B2
公开(公告)日：2019-02-19
申请号：US15686968
申请日：2017-08-25
Inventor： Graeme Gordon Mackay , Jonathan Timothy Wigner , Gordon Richard McLeod
Abstract: An integrated circuit for digital signal routing. The integrated circuit has analog and digital inputs and outputs, including digital interfaces for connection to other integrated circuits. Inputs, including the digital interfaces, act as data sources. Outputs, including the digital interfaces, act as data destinations. The integrated circuit also includes signal processing blocks, which can act as data sources and data destinations. Signal routing is achieved by means of a multiply-accumulate block, which takes data from one or more data source and, after any required scaling, generates output data for a data destination. Data from a data source is buffered for an entire period of a data sample clock so that the multiply-accumulate block can retrieve the data at any point in the period, and output data of the multiply-accumulate block is buffered for an entire period of the data sample clock so that the data destination can retrieve the data at any point in the period. Multiple signal paths can be defined by configuration data supplied to the device, either by a user, or by software. The multiply-accumulate block operates on a time division multiplexed basis, so that multiple signal paths can be processed within one period of the sample clock. Each signal path has a respective sample clock rate, and paths with different sample clock rates can be routed through the multiply-accumulate block on a time division multiplexed basis independently of each other. Thus, speech signals at 8 kHz or 16 kHz can be processed concurrently with audio data at 44.1 kHz or 48 kHz.
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