公开(公告)号：US07469332B2

公开(公告)日：2008-12-23

申请号：US11070758

申请日：2005-03-02

申请人： Claude Basso ,  Jean Louis Calvignac ,  Chih-jen Chang ,  Harm Peter Hofstee ,  Jens Leenstra ,  Hans-Werner Tast ,  Fabrice Jean Verplanken ,  Colin Beaton Verrilli

发明人： Claude Basso ,  Jean Louis Calvignac ,  Chih-jen Chang ,  Harm Peter Hofstee ,  Jens Leenstra ,  Hans-Werner Tast ,  Fabrice Jean Verplanken ,  Colin Beaton Verrilli

IPC分类号： G06F9/355

CPC分类号： G06F12/0864

摘要： Systems and methods for adaptively mapping system memory address bits into an instruction tag and an index into the cache are disclosed. More particularly, hardware and software are disclosed for observing collisions that occur for a given mapping of system memory bits into a tag and an index. Based on the observations, an optimal mapping may be determined that minimizes collisions.

摘要翻译： 公开了用于将系统存储器地址位自适应地映射到指令标签和到高速缓存中的索引的系统和方法。 更具体地，公开了用于观察对于系统存储器位给定到标签和索引的映射而出现的冲突的硬件和软件。 基于观察结果，可以确定最小化碰撞的最佳映射。

公开(公告)号：US20080222394A1

公开(公告)日：2008-09-11

申请号：US12124396

申请日：2008-05-21

申请人： Claude Basso ,  Jean Louis Calvignac ,  Chih-jen Chang ,  Gordon Taylor David ,  Harm Peter Hofstee ,  Fabrice Jean Verplanken ,  Colin Beaton Verrilli

发明人： Claude Basso ,  Jean Louis Calvignac ,  Chih-jen Chang ,  Gordon Taylor David ,  Harm Peter Hofstee ,  Fabrice Jean Verplanken ,  Colin Beaton Verrilli

IPC分类号： G06F9/30

CPC分类号： G06F9/3851 ,  G06F9/3802 ,  G06F9/4843

摘要： Systems and methods for distributing thread instructions in the pipeline of a multi-threading digital processor are disclosed. More particularly, hardware and software are disclosed for successively selecting threads in an ordered sequence for execution in the processor pipeline. If a thread to be selected cannot execute, then a complementary thread is selected for execution.

摘要翻译： 公开了在多线程数字处理器的流水线中分发线程指令的系统和方法。 更具体地，公开了硬件和软件，用于以有序序列连续选择线程以在处理器管线中执行。 如果要选择的线程无法执行，则选择补充线程执行。

公开(公告)号：US07474662B2

公开(公告)日：2009-01-06

申请号：US11119329

申请日：2005-04-29

申请人： Claude Basso ,  Jean Louis Calvignac ,  Chih-jen Chang ,  Natarajan Vaidhyanathan ,  Fabrice Jean Verplanken

发明人： Claude Basso ,  Jean Louis Calvignac ,  Chih-jen Chang ,  Natarajan Vaidhyanathan ,  Fabrice Jean Verplanken

IPC分类号： H04L12/56

CPC分类号： H04L47/623 ,  H04L47/50 ,  H04L47/568

摘要： Systems and methods for scheduling data packets in a network processor are disclosed. Embodiments provide a network processor that comprises a best-effort scheduler with a minimal calendar structure for addressing schedule control blocks. In one embodiment, a four-entry calendar structure provides for rate-limited weighted best effort scheduling. Each of a plurality of different flows has associated schedule control blocks. Schedule control blocks are stored as linked lists in a last-in-first-out buffer. Each calendar entry is associated with a different linked list by storing in the calendar entry the address of the first-out schedule control block in the linked list. Each schedule control block has a counter and is assigned a rate limit according to the bandwidth priority of the flow to which the corresponding packet belongs. Each time a schedule control block is accessed from a last-in-first-out buffer storing the linked list, the scheduler generates a scheduling event and the counter of the schedule control block is incremented. When an incremented counter of a schedule control block equals its rate limit, the schedule control block is temporarily removed from further scheduling until a time interval concludes.

摘要翻译： 公开了一种用于在网络处理器中调度数据分组的系统和方法。 实施例提供了一种网络处理器，其包括具有用于寻址日程控制块的最小日历结构的尽力而为调度器。 在一个实施例中，四入口日历结构提供速率受限加权最佳努力调度。 多个不同流中的每一个都具有相关联的调度控制块。 计划控制块作为链表存储在先进先出缓冲区中。 通过在日历条目中存储链表中的先出时间表控制块的地址来将每个日历条目与不同的链表相关联。 每个调度控制块都有一个计数器，并根据相应数据包所属的流的带宽优先级分配速率限制。 每当从存储链表的最先进先出缓冲器访问调度控制块时，调度器生成调度事件，并且调度控制块的计数器递增。 当调度控制块的递增计数器等于其速率限制时，调度控制块暂时从进一步调度中移除，直到时间间隔结束。

公开(公告)号：US07529224B2

公开(公告)日：2009-05-05

申请号：US11108485

申请日：2005-04-18

申请人： Claude Basso ,  Jean Louis Calvignac ,  Chih-jen Chang ,  Natarajan Vaidhyanathan ,  Fabrice Jean Verplanken

发明人： Claude Basso ,  Jean Louis Calvignac ,  Chih-jen Chang ,  Natarajan Vaidhyanathan ,  Fabrice Jean Verplanken

IPC分类号： H04L12/28

CPC分类号： H04L47/568 ,  H04L45/00 ,  H04L45/60 ,  H04L47/50 ,  H04L47/527

摘要： Systems and methods for scheduling data packets in a network processor are disclosed. Embodiments provide a network processor that comprises a best-effort scheduler with a minimal calendar structure for addressing schedule control blocks. In one embodiment, a three-entry calendar structure provides for weighted best effort scheduling. Each of a plurality different flows has an associated schedule control block. Schedule control blocks are stored as linked lists in a last-in-first-out buffer. Each calendar entry is associated with a different linked list by storing in the calendar entry the address of the first-out schedule control block in the linked list. Each schedule control block has a counter and is assigned a weight according to the bandwidth priority of the flow to which the corresponding packet belongs. Each time a schedule control block is accessed from a last-in-first-out buffer storing the linked list, the scheduler generates a scheduling event and the counter of the schedule control block is incremented. When an incremented counter of a schedule control block equals its weight, the schedule control block is temporarily removed from further scheduling.

摘要翻译： 公开了一种用于在网络处理器中调度数据分组的系统和方法。 实施例提供了一种网络处理器，其包括具有用于寻址日程控制块的最小日历结构的尽力而为调度器。 在一个实施例中，三入口日历结构提供加权最佳努力调度。 多个不同的流中的每一个具有相关的进度控制块。 计划控制块作为链表存储在先进先出缓冲区中。 通过在日历条目中存储链表中的先出时间表控制块的地址来将每个日历条目与不同的链表相关联。 每个调度控制块具有计数器，并根据相应分组所属的流的带宽优先级分配权重。 每当从存储链表的最先进先出缓冲器访问调度控制块时，调度器生成调度事件，并且调度控制块的计数器递增。 当调度控制块的递增计数器等于其权重时，调度控制块暂时从进一步调度中移除。

公开(公告)号：US20080147995A1

公开(公告)日：2008-06-19

申请号：US12039304

申请日：2008-02-28

申请人： Claude Basso ,  Jean Louis Calvignac ,  Chih-jen Chang ,  Fabrice Jean Verplanken

发明人： Claude Basso ,  Jean Louis Calvignac ,  Chih-jen Chang ,  Fabrice Jean Verplanken

IPC分类号： G06F12/00

CPC分类号： H04L49/901 ,  H04L49/252 ,  H04L49/30 ,  H04L49/90 ,  H04L69/12 ,  H04L69/22

摘要： Systems and methods for implementing multi-frame control blocks in a network processor are disclosed. Embodiments include systems and methods to reduce long latency memory access to less expensive memory such as DRAM. As a network processor in a network receives packets of data, the network processor forms a frame control block for each packet. The frame control block contains a pointer to a memory location where the packet data is stored, and is thereby associated with the packet. The network processor associates a plurality of frame control blocks together in a table control block that is stored in a control store. Each table control block comprises a pointer to a memory location of a next table control block in a chain of table control blocks. Because frame control blocks are stored and accessed in table control blocks, less frequent memory accesses may be needed to keep up with the frame rate of packet transmission.

摘要翻译： 公开了一种用于在网络处理器中实现多帧控制块的系统和方法。 实施例包括用于减少长时间存储器访问到诸如DRAM之类的便宜的存储器的系统和方法。 随着网络中的网络处理器接收数据包，网络处理器为每个数据包形成帧控制块。 帧控制块包含指向存储分组数据的存储器位置的指针，并且因此与分组相关联。 网络处理器将存储在控制存储器中的表控制块中的多个帧控制块相关联。 每个表控制块包括指向表控制块链中的下一个表控制块的存储器位置的指针。 由于帧控制块在表控制块中被存储和访问，因此可能需要较少频率的存储器访问以跟上分组传输的帧速率。

公开(公告)号：US07376809B2

公开(公告)日：2008-05-20

申请号：US11076218

申请日：2005-03-09

申请人： Claude Basso ,  Jean Louis Calvignac ,  Chih-jen Chang ,  Fabrice Jean Verplanken

发明人： Claude Basso ,  Jean Louis Calvignac ,  Chih-jen Chang ,  Fabrice Jean Verplanken

IPC分类号： G06F12/02

CPC分类号： H04L49/901 ,  H04L49/252 ,  H04L49/30 ,  H04L49/90 ,  H04L69/12 ,  H04L69/22

摘要： Systems and methods for implementing multi-frame control blocks in a network processor are disclosed. Embodiments include systems and methods to reduce long latency memory access to less expensive memory such as DRAM. As a network processor in a network receives packets of data, the network processor forms a frame control block for each packet. The frame control block contains a pointer to a memory location where the packet data is stored, and is thereby associated with the packet. The network processor associates a plurality of frame control blocks together in a table control block that is stored in a control store. Each table control block comprises a pointer to a memory location of a next table control block in a chain of table control blocks. Because frame control blocks are stored and accessed in table control blocks, less frequent memory accesses may be needed to keep up with the frame rate of packet transmission.

摘要翻译： 公开了一种用于在网络处理器中实现多帧控制块的系统和方法。 实施例包括用于减少长时间存储器访问到诸如DRAM之类的便宜的存储器的系统和方法。 随着网络中的网络处理器接收数据包，网络处理器为每个数据包形成帧控制块。 帧控制块包含指向存储分组数据的存储器位置的指针，并且因此与分组相关联。 网络处理器将存储在控制存储器中的表控制块中的多个帧控制块相关联。 每个表控制块包括指向表控制块链中的下一个表控制块的存储器位置的指针。 由于帧控制块在表控制块中被存储和访问，因此可能需要较少频率的存储器访问以跟上分组传输的帧速率。

公开(公告)号：US07603539B2

公开(公告)日：2009-10-13

申请号：US12039304

申请日：2008-02-28

申请人： Claude Basso ,  Jean Louis Calvignac ,  Chih-jen Chang ,  Fabrice Jean Verplanken

发明人： Claude Basso ,  Jean Louis Calvignac ,  Chih-jen Chang ,  Fabrice Jean Verplanken

IPC分类号： G06F12/00

CPC分类号： H04L49/901 ,  H04L49/252 ,  H04L49/30 ,  H04L49/90 ,  H04L69/12 ,  H04L69/22

摘要： Systems and methods for implementing multi-frame control blocks in a network processor are disclosed. Embodiments include systems and methods to reduce long latency memory access to less expensive memory such as DRAM. As a network processor in a network receives packets of data, the network processor forms a frame control block for each packet. The frame control block contains a pointer to a memory location where the packet data is stored, and is thereby associated with the packet. The network processor associates a plurality of frame control blocks together in a table control block that is stored in a control store. Each table control block comprises a pointer to a memory location of a next table control block in a chain of table control blocks. Because frame control blocks are stored and accessed in table control blocks, less frequent memory accesses may be needed to keep up with the frame rate of packet transmission.

摘要翻译： 公开了一种用于在网络处理器中实现多帧控制块的系统和方法。 实施例包括用于减少长时间存储器访问到诸如DRAM之类的便宜的存储器的系统和方法。 随着网络中的网络处理器接收数据包，网络处理器为每个数据包形成帧控制块。 帧控制块包含指向存储分组数据的存储器位置的指针，并且因此与分组相关联。 网络处理器将存储在控制存储器中的表控制块中的多个帧控制块相关联。 每个表控制块包括指向表控制块链中的下一个表控制块的存储器位置的指针。 由于帧控制块在表控制块中被存储和访问，因此可能需要较少频率的存储器访问以跟上分组传输的帧速率。

公开(公告)号：US20120204190A1

公开(公告)日：2012-08-09

申请号：US13365778

申请日：2012-02-03

申请人： Claude Basso ,  Jean L. Calvignac ,  Chih-jen Chang ,  Philippe Damon ,  Natarajan Vaidhyanathan ,  Fabrice J. Verplanken ,  Colin B. Verrilli

发明人： Claude Basso ,  Jean L. Calvignac ,  Chih-jen Chang ,  Philippe Damon ,  Natarajan Vaidhyanathan ,  Fabrice J. Verplanken ,  Colin B. Verrilli

IPC分类号： G06F9/46

CPC分类号： G06F9/546 ,  G06F9/544

摘要： A mechanism is provided for merging in a network processor results from a parser and results from an external coprocessor providing processing support requested by said parser. The mechanism enqueues in a result queue both parser results needing to be merged with a coprocessor result and parser results which have no need to be merged with a coprocessor result. An additional queue is used to enqueue the addresses of the result queue where the parser results are stored. The result from the coprocessor is received in a simple response register. The coprocessor result is read by the result queue management logic from the response register and merged to the corresponding incomplete parser result read in the result queue at the address enqueued in the additional queue.

摘要翻译： 提供了一种机制，用于在来自解析器的网络处理器结果和来自提供由所述解析器请求的处理支持的外部协处理器的结果中合并。 结果队列中的机制排队，解析器结果需要与协处理器结果合并，并且不需要与协处理器结果合并的解析器结果。 使用一个附加队列来排列存储解析器结果的结果队列的地址。 协处理器的结果是在简单的响应寄存器中接收的。 协处理器结果由响应寄存器的结果队列管理逻辑读取，并被合并到在附加队列中排队的地址的结果队列中读取的相应的不完整解析器结果。

公开(公告)号：US20120192190A1

公开(公告)日：2012-07-26

申请号：US13011663

申请日：2011-01-21

申请人： Claude Basso ,  Jean L. Calvignac ,  Chih-jen Chang ,  Philippe Damon ,  Natarajan Vaidhyanathan ,  Fabrice J. Verplanken ,  Colin B. Verrilli

发明人： Claude Basso ,  Jean L. Calvignac ,  Chih-jen Chang ,  Philippe Damon ,  Natarajan Vaidhyanathan ,  Fabrice J. Verplanken ,  Colin B. Verrilli

IPC分类号： G06F9/46

CPC分类号： G06F15/1735

摘要： A host Ethernet adapter (HEA) and method of managing network communications is provided. The HEA includes a host interface configured for communication with a multi-core processor over a processor bus. The host interface comprises a receive processing element including a receive processor, a receive buffer and a scheduler for dispatching packets from the receive buffer to the receive processor; a send processing element including a send processor and a send buffer; and a completion queue scheduler (CQS) for dispatching completion queue elements (CQE) from the head of the completion queue (CQ) to threads of the multi-core processor in a network node mode. The method comprises operatively coupling an Ethernet adapter to a multi-core processor system via a processor bus, selectively assigning a first plurality of packets to a first queue pair for servicing in an endpoint mode, running a device driver on the multi-core processing system, the device driver controlling the servicing of the first queue pair by dispatching the first plurality of packets to only one processor core of the multi-core processor system, selectively assigning a second plurality of packets to a second queue pair for servicing in a network node mode; and the Ethernet adapter controlling the servicing of the second queue pair by dispatching the second plurality of packets to multiple processor threads.

摘要翻译： 提供主机以太网适配器（HEA）和管理网络通信的方法。 HEA包括被配置为通过处理器总线与多核处理器进行通信的主机接口。 所述主机接口包括接收处理元件，所述接收处理元件包括接收处理器，接收缓冲器和用于从所述接收缓冲器向所述接收处理器分发分组的调度器; 包括发送处理器和发送缓冲器的发送处理元件; 以及用于从完成队列（CQ）的头部将网络节点模式中的多核处理器的线程调度完成队列元素（CQE）的完成队列调度器（CQS）。 该方法包括经由处理器总线可操作地将以太网适配器耦合到多核处理器系统，选择性地将第一多个分组分配到第一队列对以在端点模式下进行服务，在多核处理系统上运行设备驱动程序 所述设备驱动程序通过将所述第一多个分组分派到所述多核处理器系统的一个处理器核心来控制所述第一队列对的服务，选择性地将第二多个分组分配给第二队列对以在网络节点中进行服务 模式; 以及所述以太网适配器通过将所述第二多个分组分派到多个处理器线程来控制所述第二队列对的服务。

公开(公告)号：US07715428B2

公开(公告)日：2010-05-11

申请号：US11669419

申请日：2007-01-31

申请人： Claude Basso ,  Jean L. Calvignac ,  Chih-jen Chang ,  Philippe Damon ,  Herman D. Dierks, Jr. ,  Christoph Raisch ,  Jan-Bernd Themann ,  Natarajan Vaidhyanathan ,  Fabrice J. Verplanken ,  Colin B. Verrilli

发明人： Claude Basso ,  Jean L. Calvignac ,  Chih-jen Chang ,  Philippe Damon ,  Herman D. Dierks, Jr. ,  Christoph Raisch ,  Jan-Bernd Themann ,  Natarajan Vaidhyanathan ,  Fabrice J. Verplanken ,  Colin B. Verrilli

IPC分类号： H04L12/66 ,  H04J3/16 ,  H04J3/22

CPC分类号： H04L47/50

摘要： Mechanisms for processing of communications between data processing devices are provided. With the mechanisms of the illustrative embodiments, a set of techniques that enables sustaining media speed by distributing transmit and receive-side processing over multiple processing cores is provided. In addition, these techniques also enable designing multi-threaded network interface controller (NIC) hardware that efficiently hides the latency of direct memory access (DMA) operations associated with data packet transfers over an input/output (I/O) bus. Multiple processing cores may operate concurrently using separate instances of a communication protocol stack and device drivers to process data packets for transmission with separate hardware implemented send queue managers in a network adapter processing these data packets for transmission. Multiple hardware receive packet processors in the network adapter may be used, along with a flow classification engine, to route received data packets to appropriate receive queues and processing cores for processing.

摘要翻译： 提供了用于处理数据处理设备之间的通信的机制。 利用说明性实施例的机制，提供了一组通过在多个处理核上分发发送和接收侧处理来维持媒体速度的技术。 此外，这些技术还可以设计出多线程网络接口控制器（NIC）硬件，可有效地隐藏通过输入/输出（I / O）总线传输数据分组的直接存储器访问（DMA）操作的延迟。 多个处理核心可以使用通信协议栈和设备驱动程序的单独实例同时运行，以处理用于传输的数据分组，其中单独的硬件实现了处理这些数据分组以进行传输的网络适配器中的发送队列管理器。 可以使用网络适配器中的多个硬件接收分组处理器以及流分类引擎将接收到的数据分组路由到适当的接收队列和处理核心进行处理。