公开(公告)号：US20210058228A1

公开(公告)日：2021-02-25

申请号：US17009361

申请日：2020-09-01

Applicant: Cryptography Research, Inc.

Inventor： Jean-Michel Cioranesco ,  Elena Trichina ,  Elke De Mulder ,  Matthew Pond Baker

IPC: H04L9/00 ,  H04L9/14 ,  H04L9/06

Abstract: Systems and methods for protecting block cipher computation operations, from external monitoring attacks. An example apparatus for implementing a block cipher may comprise: a first register configured to store a first pre-computed mask value represented by a combination of a first random value and a second random value; a second register configured to store an output mask value, wherein the output mask value is an inverse permutation function of the first random value; a third register configured to store a second pre-computed mask value represented by a combination the first pre-computed mask value and a permutation function of the output mask value; a fourth register configured to store an input mask value, wherein the input mask value is a combination of an expansion function of the first random value and a key mask value; a non-linear transformation circuit configured to apply the expansion function to a masked round state, perform a non-linear transformation of a combination of a masked key with an output of the expansion function, and apply the permutation function to the output of the non-linear transformation, wherein the non-linear transformation is defined using the input mask value stored in the fourth register and the output mask value stored in the second register; and two round feedback circuits configured to swap the masked round state produced by the non-linear transformation and combine the masked round state with the first pre-computed mask value stored in the first register and the second pre-computed mask value stored in the third register.

公开(公告)号：US20200067695A1

公开(公告)日：2020-02-27

申请号：US16666017

申请日：2019-10-28

Applicant: Cryptography Research, Inc.

Inventor： Matthew Pond Baker ,  Elena Trichina ,  Jean-Michel Cioranesco ,  Michael Hutter

IPC: H04L9/06 ,  H04L9/00 ,  G06F21/60 ,  G06F21/75 ,  G06F21/55

Abstract: An integrated circuit may implement a masked substitution box that includes substitution function components, a decoder, and a logic component. Each of the substitution function components may receive a same input value and a different mask value and may generate a respective output mask value based on the same input value and respective different mask value The decoder may receive an input mask value and generate a decoded output value that is based on the received input mask value. The logic component may select one of the output mask values from one of the substitution function components based on the decoded output value.

公开(公告)号：US20180062828A1

公开(公告)日：2018-03-01

申请号：US15682881

申请日：2017-08-22

Applicant: Cryptography Research, Inc.

Inventor： Jean-Michel Cioranesco ,  Elena Trichina ,  Elke De Mulder ,  Matthew Pond Baker

IPC: H04L9/00 ,  H04L9/14 ,  H04L9/06

Abstract: Systems and methods for protecting block cipher computation operations, from external monitoring attacks. An example apparatus for implementing a block cipher may comprise: a first register configured to store a first pre-computed mask value represented by a combination of a first random value and a second random value; a second register configured to store an output mask value, wherein the output mask value is an inverse permutation function of the first random value; a third register configured to store a second pre-computed mask value represented by a combination the first pre-computed mask value and a permutation function of the output mask value; a fourth register configured to store an input mask value, wherein the input mask value is a combination of an expansion function of the first random value and a key mask value; a non-linear transformation circuit configured to apply the expansion function to a masked round state, perform a non-linear transformation of a combination of a masked key with an output of the expansion function, and apply the permutation function to the output of the non-linear transformation, wherein the non-linear transformation is defined using the input mask value stored in the fourth register and the output mask value stored in the second register; and two round feedback circuits configured to swap the masked round state produced by the non-linear transformation and combine the masked round state with the first pre-computed mask value stored in the first register and the second pre-computed mask value stored in the third register.

公开(公告)号：US20170061121A1

公开(公告)日：2017-03-02

申请号：US15245507

申请日：2016-08-24

Applicant: Cryptography Research, Inc

Inventor： Roberto Rivoir ,  Elke De Mulder ,  Jean-Michel Cioranesco

IPC: G06F21/55

CPC classification number: G06F21/755 ,  G06F2221/034

Abstract: A side-channel attack resistant circuit topology for performing logic functions. This topology includes combinatorial logic to perform the at least one logic function. A logic input selector alternately supplies, in response to a first timing reference signal, an input to the combinatorial logic with noise generating input values and valid input values. A first latch input selector alternately supplies, in response to the first timing reference signal, a first memory element input with noise generating input values and valid logic output values. The valid logic output values are received from the combinatorial logic. A first memory element latches the valid logic output values in response to a second timing reference signal.

Abstract translation: 用于执行逻辑功能的侧信道攻击电路拓扑。 该拓扑包括用于执行至少一个逻辑功能的组合逻辑。 逻辑输入选择器响应于第一定时参考信号交替地提供具有噪声产生输入值和有效输入值的组合逻辑的输入。 第一锁存器输入选择器响应于第一定时参考信号交替地提供输入噪声产生输入值和有效逻辑输出值的第一存储器元件。 从组合逻辑接收有效的逻辑输出值。 响应于第二定时参考信号，第一存储器元件锁存有效的逻辑输出值。