公开(公告)号：US11163531B2

公开(公告)日：2021-11-02

申请号：US16447966

申请日：2019-06-21

Applicant: DSP GROUP LTD.

Inventor： Moshe Haiut ,  Assaf Ganor

IPC: G06F7/544 ,  G06F7/498

Abstract: A method and a MAC unit that may include accumulation unit and a multiplier. A accumulation unit that includes a first part, a second part and a third part. The first part may calculate a truncated sum. The second part may be configured to (a) receive, during each calculation cycle, a carry out of an add operation performed during a calculation cycle, (b) receive a sign bit of an intermediate product calculated during the calculation cycle; and (c) calculate, by the counter logic, a counter logic value, and (d) convert, after a start of a last calculation cycle of the calculation cycles, an output value of the counter logic to an intermediate value having a two's complement format. The third part may be configured to calculate an output value of the MAC unit based on the intermediate value and a truncated sum calculated by the first part of the accumulation unit.