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1.发明授权Efficient drift avoidance mechanism for synchronous and asynchronous digital sample rate converters 有权用于同步和异步数字采样率转换器的高效漂移避免机制公开(公告)号：US09209783B2
公开(公告)日：2015-12-08
申请号：US14613388
申请日：2015-02-04
Applicant: DSP Group LTD.
Inventor： Yosef Bendel , Eyal Rosin , Assaf Ganor
CPC classification number: H03H17/0657 , G06F5/06 , G10L19/00 , G10L19/008 , G10L21/04 , H03H17/0642 , H03H17/0664 , H03H17/0685 , H04L7/0037 , H04L7/033 , H04L7/0337 , H04L27/2657
Abstract: A device, comprising a first interpolator that is configured to (a) receive, at a first clock rate, a first signal having a first sampling rate and (b) output, at a second clock rate, a second signal having a first desired sampling rate average; wherein the first interpolator comprises: a first buffer for storing the first signal; and a first fractional sampling ratio circuit that is configured to generate a first pattern of fixed point values, wherein an average value of the first pattern corresponds to a first desired sampling rate ratio between the first desired sampling rate average and the first sampling rate.
Abstract translation: 一种设备，包括第一内插器，其被配置为（a）以第一时钟速率接收具有第一采样率的第一信号，并且（b）以第二时钟速率输出具有第一期望采样的第二信号 速率平均 其中所述第一内插器包括：用于存储所述第一信号的第一缓冲器; 以及第一分数采样比电路，其被配置为产生固定点值的第一图案，其中所述第一图案的平均值对应于所述第一期望采样率平均值与所述第一采样率之间的第一期望采样率比。
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公开(公告)号：US20200313246A1
公开(公告)日：2020-10-01
申请号：US16808422
申请日：2020-03-04
Applicant: DSP Group Ltd.
Inventor： Assaf Ganor , Tzahi Shalit , Levi Schultz
Abstract: A coin cell powered device that includes a unit and one or more interfaces that are configured to interface between the unit, the cell coin and an external capacitor. The unit may include a regulator, a transmitter and a charge pump. The transmitter is configured to transmit signals during a transmission period while receiving power from the regulator, the power originated from the external capacitor. The charge pump is configured to perform, during a charging period, a charging process for charging the external capacitor to a charged voltage that exceeds a voltage of the cell coin, wherein the charging process may include iterations of (a) charging a charge pump capacitor by the coin cell, and (b) discharging the charge pump capacitor thereby charging the external capacitor. The capacitance of the charge pump capacitor is a fraction of a capacitance of the external capacitor. The duration of the charging period exceeds a duration of the transmission period.
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公开(公告)号：US20200273486A1
公开(公告)日：2020-08-27
申请号：US16740795
申请日：2020-01-13
Applicant: DSP Group Ltd.
Inventor： Assaf Ganor , Ori Elyada
IPC: G10L25/84 , G10K11/178
Abstract: A method for voice detection, the method may include (a) generating an in-ear signal that represents a signal sensed by an in-ear microphone and fed to a feedback active noise cancellation (ANC) circuit; (b) generating at least one additional signal, based on at least one out of a playback signal and a pickup signal sensed by a voice pickup microphone; and (c) generating a voice indicator based on the in-ear signal and the at least one additional signal.
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4.发明申请Efficient Drift Avoidance Mechanism for Synchronous and asynchronous Digital Sample Rate Converters 有权用于同步和异步数字采样率转换器的高效漂移避免机制公开(公告)号：US20150244349A1
公开(公告)日：2015-08-27
申请号：US14613388
申请日：2015-02-04
Applicant: DSP Group LTD.
Inventor： Yosef Bendel , Eyal Rosin , Assaf Ganor
IPC: H03H17/06
CPC classification number: H03H17/0657 , G06F5/06 , G10L19/00 , G10L19/008 , G10L21/04 , H03H17/0642 , H03H17/0664 , H03H17/0685 , H04L7/0037 , H04L7/033 , H04L7/0337 , H04L27/2657
Abstract: A device, comprising a first interpolator that is configured to (a) receive, at a first clock rate, a first signal having a first sampling rate and (b) output, at a second clock rate, a second signal having a first desired sampling rate average; wherein the first interpolator comprises: a first buffer for storing the first signal; and a first fractional sampling ratio circuit that is configured to generate a first pattern of fixed point values, wherein an average value of the first pattern corresponds to a first desired sampling rate ratio between the first desired sampling rate average and the first sampling rate.
Abstract translation: 一种设备，包括第一内插器，其被配置为（a）以第一时钟速率接收具有第一采样率的第一信号，并且（b）以第二时钟速率输出具有第一期望采样的第二信号 速率平均 其中所述第一内插器包括：用于存储所述第一信号的第一缓冲器; 以及第一分数采样比电路，其被配置为产生固定点值的第一图案，其中所述第一图案的平均值对应于所述第一期望采样率平均值与所述第一采样率之间的第一期望采样率比。
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公开(公告)号：US20240088459A1
公开(公告)日：2024-03-14
申请号：US18472423
申请日：2023-09-22
Applicant: DSP Group Ltd.
Inventor： Assaf Ganor , Tzahi Shalit , Levi Schultz
CPC classification number: H01M10/4264 , H01M10/0436 , H02J7/345
Abstract: A coin cell powered device that includes a unit and one or more interfaces that are configured to interface between the unit, the cell coin and an external capacitor. The unit may include a regulator, a transmitter and a charge pump. The transmitter is configured to transmit signals during a transmission period while receiving power from the regulator, the power originated from the external capacitor. The charge pump is configured to perform, during a charging period, a charging process for charging the external capacitor to a charged voltage that exceeds a voltage of the cell coin, wherein the charging process may include iterations of (a) charging a charge pump capacitor by the coin cell, and (b) discharging the charge pump capacitor thereby charging the external capacitor. The capacitance of the charge pump capacitor is a fraction of a capacitance of the external capacitor. The duration of the charging period exceeds a duration of the transmission period.
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Patent Agency Ranking
公开(公告)号：US20200034117A1
公开(公告)日：2020-01-30
申请号：US16447966
申请日：2019-06-21
Applicant: DSP GROUP LTD.
Inventor： MOSHE HAIUT , Assaf Ganor
Abstract: A method and a MAC unit that may include accumulation unit and a multiplier. A accumulation unit that includes a first part, a second part and a third part. The first part may calculate a truncated sum. The second part may be configured to (a) receive, during each calculation cycle, a carry out of an add operation performed during a calculation cycle, (b) receive a sign bit of an intermediate product calculated during the calculation cycle; and (c) calculate, by the counter logic, a counter logic value, and (d) convert, after a start of a last calculation cycle of the calculation cycles, an output value of the counter logic to an intermediate value having a two's complement format. The third part may be configured to calculate an output value of the MAC unit based on the intermediate value and a truncated sum calculated by the first part of the accumulation unit.
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公开(公告)号：US09673820B2
公开(公告)日：2017-06-06
申请号：US14697644
申请日：2015-04-28
Applicant: DSP Group LTD.
Inventor： Assaf Ganor
CPC classification number: H03K19/018507 , H03K3/012 , H03K3/013 , H03K3/037 , H03K5/00 , H03K19/20 , H03K2005/00013
Abstract: A scheme is described that provides for a low latency, glitch free chip interface that does not require a clock. This invention handles input transitions that are skewed and also input transitions that are momentary. A change in an input state initiates a pulse that propagates through the system and samples the new input state after a delay. If there is a difference between the sampled input state and the present input state, then a new pulse is initiated in order to avoid any illegal transitions at the output.
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公开(公告)号：US20150333739A1
公开(公告)日：2015-11-19
申请号：US14697644
申请日：2015-04-28
Applicant: DSP Group LTD.
Inventor： Assaf Ganor
CPC classification number: H03K19/018507 , H03K3/012 , H03K3/013 , H03K3/037 , H03K5/00 , H03K19/20 , H03K2005/00013
Abstract: A scheme is described that provides for a low latency, glitch free chip interface that does not require a clock. This invention handles input transitions that are skewed and also input transitions that are momentary. A change in an input state initiates a pulse that propagates through the system and samples the new input state after a delay. If there is a difference between the sampled input state and the present input state, then a new pulse is initiated in order to avoid any illegal transitions at the output.
Abstract translation: 描述了一种提供不需要时钟的低延迟，无故障芯片接口的方案。 本发明处理倾斜的输入转换以及瞬时的输入转换。 输入状态的改变会启动一个脉冲，通过系统进行传播，并在延迟后采样新的输入状态。 如果采样输入状态和当前输入状态之间存在差异，则启动新的脉冲，以避免输出端的任何非法转换。
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公开(公告)号：US11811026B2
公开(公告)日：2023-11-07
申请号：US16808422
申请日：2020-03-04
Applicant: DSP Group Ltd.
Inventor： Assaf Ganor , Tzahi Shalit , Levi Schultz
CPC classification number: H01M10/4264 , H01M10/0436 , H02J7/345
Abstract: A coin cell powered device includes a regulator, a transmitter and a charge pump. The transmitter is configured to transmit signals during a transmission period while receiving power from the regulator, the power originated from an external capacitor. The charge pump is configured to perform, during a charging period, a charging process for charging the external capacitor to a charged voltage that exceeds a voltage of a cell coin, wherein the charging process may include iterations of (a) charging a charge pump capacitor by the coin cell, and (b) discharging the charge pump capacitor thereby charging the external capacitor. The capacitance of the charge pump capacitor is a fraction of a capacitance of the external capacitor. The duration of the charging period exceeds a duration of the transmission period.
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公开(公告)号：US11222654B2
公开(公告)日：2022-01-11
申请号：US16740795
申请日：2020-01-13
Applicant: DSP Group Ltd.
Inventor： Assaf Ganor , Ori Elyada
IPC: G10L25/84 , G10K11/178
Abstract: A method for voice detection, the method may include (a) generating an in-ear signal that represents a signal sensed by an in-ear microphone and fed to a feedback active noise cancellation (ANC) circuit; (b) generating at least one additional signal, based on at least one out of a playback signal and a pickup signal sensed by a voice pickup microphone; and (c) generating a voice indicator based on the in-ear signal and the at least one additional signal.
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