公开(公告)号：US5136691A

公开(公告)日：1992-08-04

申请号：US146020

申请日：1988-01-20

Applicant: Gigy Baror

Inventor： Gigy Baror

IPC: G06F9/38 ,  G06F12/08 ,  G06F15/78

CPC classification number: G06F12/0888 ,  G06F12/0837 ,  G06F12/0848 ,  G06F15/7835

Abstract: Methods and apparatus are disclosed for supporting the caching of interlock variables in cache memory units employed in multiprocessor and/or multitasking environments. The preferred embodiment of the invention includes methods and apparatus for selectively treating interlock variables as cachable or non-cachable. The disclosed methods and apparatus are suitable for supporting high speed data and instruction processing applications in both RISC and non-RISC architecture environments, can be integrated on a single chip and allows for better performance and utilization of the computer system bus structure since most of the interlock variable accesses are faster and do not appear on the memory bus (only in the cache).