公开(公告)号：US06405273B1

公开(公告)日：2002-06-11

申请号：US09192170

申请日：1998-11-13

申请人： Rod G. Fleck ,  Klaus Oberlaender ,  Gigy Baror ,  Alfred Eder ,  Le Trong Nguyen

发明人： Rod G. Fleck ,  Klaus Oberlaender ,  Gigy Baror ,  Alfred Eder ,  Le Trong Nguyen

IPC分类号： G06F1300

CPC分类号： G06F13/1678

摘要： A data processing unit is disclosed with a register file having a plurality of registers. A memory having a plurality of n-bit input/output ports, and a coupling unit for coupling the memory with the register file, a memory address and select unit for addressing the memory banks are provided. The coupling unit comprises a bus having a bus width of at least 2n-bits forming at least a first and second sub-bus, first couplers for coupling each memory bank or the register file selectively with one of the sub-busses, and second couplers for coupling the register file or the memory banks with the bus.

摘要翻译： 公开了具有多个寄存器的寄存器文件的数据处理单元。 提供具有多个n位输入/输出端口的存储器，以及用于将存储器与寄存器文件耦合的耦合单元，用于寻址存储体的存储器地址和选择单元。 耦合单元包括具有形成至少第一和第二子总线的至少2n位的总线宽度的总线，用于将每个存储体或寄存器文件选择性地耦合到子总线之一的第一耦合器和第二耦合器 用于将寄存器文件或存储体与总线耦合。

公开(公告)号：US6076159A

公开(公告)日：2000-06-13

申请号：US928766

申请日：1997-09-12

申请人： Rod G. Fleck ,  Ole H. Moller ,  Gigy Baror

发明人： Rod G. Fleck ,  Ole H. Moller ,  Gigy Baror

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F9/00

CPC分类号： G06F9/3891 ,  G06F9/3013 ,  G06F9/30141 ,  G06F9/381 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3859 ,  G06F9/3885 ,  G06F9/3889

摘要： A data processor is disclosed which comprises a first pipeline for decoding and executing data instructions, a second pipeline for decoding and executing address instructions, a unit for issuing multiple instructions to the pipelines, a first set of registers being coupled with the first pipeline, and a second set of registers being coupled with the second pipeline, wherein first and second pipeline process data in parallel.

摘要翻译： 公开了一种数据处理器，其包括用于解码和执行数据指令的第一流水线，用于解码和执行地址指令的第二流水线，用于向流水线发出多个指令的单元，与第一管线耦合的第一组寄存器，以及 与所述第二管道耦合的第二组寄存器，其中并行地进行第一和第二管线处理数据。

公开(公告)号：US4926323A

公开(公告)日：1990-05-15

申请号：US163917

申请日：1988-03-03

申请人： Gigy Baror ,  Brian W. Case ,  Rod G. Fleck ,  Philip M. Freidin ,  Smeeta Gupta ,  William M. Johnson ,  Cheng-Gang Kong ,  Ole H. Moller ,  Timothy A. Olson ,  David I. Sorensen

发明人： Gigy Baror ,  Brian W. Case ,  Rod G. Fleck ,  Philip M. Freidin ,  Smeeta Gupta ,  William M. Johnson ,  Cheng-Gang Kong ,  Ole H. Moller ,  Timothy A. Olson ,  David I. Sorensen

IPC分类号： G06F9/38

CPC分类号： G06F9/3804 ,  G06F9/3867

摘要： A streamlined instruction processor processes data in response to a program composed of prespecified instructions in pipeline cycles. The processor comprises an instruction fetch unit, including an instruction interface adapted for connection to an instruction memory and for fetching instructions from the instruction memory. The instruction fetch unit includes an instruction prefetch buffer coupled to the instruction interface for buffering a sequence of instructions supplied to the instruction interface. A branch target cache is coupled with the prefetch buffer for storing sets of instructions retrieved from a corresponding set of locations in the instruction memory, having sequential instruction addresses. The first instruction in each such set is a branch target instruction in the program.In addition, an execution unit including a data interface adapted for connection to the data memory, executes the instructions in pipeline cycles. The execution unit includes a storage facility, coupled to the data interface, for storing data in a file of data locations identified by file addresses. The storage facility includes at least two read ports and one write port operable in response to file addresses. An addressing unit coupled to receive the instructions from the instruction register, supplies the file addresses to the read ports and the write port under program control. In addition, the addressing unit is operable in response to a stack pointer providing dynamic allocation of the file of data locations to processes within the program.A memory management unit is coupled to the data interface. The memory management unit includes an address interface adapted for connection to the data memory and the instruction memory for supplying instruction addresses to the instruction memory and data addresses to the data memory, in a simple single access mode, a pipeline mode and a burst mode.

摘要翻译： 精简指令处理器响应于由流水线循环中的预先指定组成的程序来处理数据。 处理器包括指令提取单元，其包括适于连接到指令存储器并用于从指令存储器取出指令的指令接口。 指令提取单元包括指令预取缓冲器，其耦合到指令接口，用于缓冲提供给指令接口的指令序列。 分支目标高速缓冲存储器与预取缓冲器耦合，用于存储从指令存储器中的对应的一组位置检索的具有顺序指令地址的指令集。 每个这样的集合中的第一条指令是程序中的分支目标指令。 此外，包括适于连接到数据存储器的数据接口的执行单元在流水线循环中执行指令。 执行单元包括耦合到数据接口的存储设备，用于将数据存储在由文件地址标识的数据位置的文件中。 存储设备包括至少两个读端口和一个可响应文件地址操作的写端口。 耦合以从指令寄存器接收指令的寻址单元，在程序控制下将文件地址提供给读端口和写端口。 此外，寻址单元响应于堆栈指针提供动态分配数据位置文件到程序内的进程而可操作。 存储器管理单元耦合到数据接口。 存储器管理单元包括适于连接到数据存储器的地址接口和用于以简单的单次访问模式，流水线模式和突发模式向指令存储器提供指令地址和数据存储器的指令存储器。

公开(公告)号：US5627992A

公开(公告)日：1997-05-06

申请号：US434494

申请日：1995-05-04

申请人： Gigy Baror

发明人： Gigy Baror

IPC分类号： G06F12/08 ,  G06F12/10 ,  G06F12/00

CPC分类号： G06F12/0837 ,  G06F12/1027

摘要： A computer system having a cache memory subsystem which allows flexible setting of caching policies on a page basis and a line basis. A cache block status field is provided for each cache block to indicate the cache block's state, such as shared or exclusive. The cache block status field controls whether the cache control unit operates in a write-through write mode or in a copy-back write mode when a write hit access to the block occurs. The cache block status field may be updated by either a TLB write policy field contained within a translation look-aside buffer entry which corresponds to the page of the access, or by a second input independent of the TLB entry which may be provided from the system on a line basis.

摘要翻译： 一种具有高速缓冲存储器子系统的计算机系统，其允许以页面为基础和线基于灵活地设置高速缓存策略。 为每个高速缓存块提供高速缓存块状态字段以指示高速缓存块的状态，例如共享或排他。 高速缓存块状态字段控制当写入命中访问块时，高速缓存控制单元是以直写写入模式还是复制写入模式操作。 高速缓存块状态字段可以由包含在对应于访问的页面的转换后备缓冲器条目中的TLB写策略字段或独立于可从系统提供的TLB条目的第二输入来更新 在线的基础上

公开(公告)号：US5025366A

公开(公告)日：1991-06-18

申请号：US146009

申请日：1988-01-20

申请人： Gigy Baror

发明人： Gigy Baror

IPC分类号： G06F9/38 ,  G06F12/08

CPC分类号： G06F12/0893 ,  G06F12/0862 ,  G06F2212/601

摘要： Methods and apparatus are disclosed for realizing an integrated cache unit which may be flexibly used for cache system design. The preferred embodiment of the invention comprises both a cache memory and a cache controller on a single chip. In accordance with an alternative embodiment of the invention, the cache memory may be externally located. Flexible cache system design is achieved by the specification of desired cache features through the setting of appropriate cache option bits. The disclosed methods and apparatus support this user oriented approach to flexible system design. The actual setting of option bits may be performed under software control and allows a high performance cache system to be designed with few parts, at low cost and with the ability to perform with high efficiency.

公开(公告)号：US5185878A

公开(公告)日：1993-02-09

申请号：US626239

申请日：1990-12-12

申请人： Gigy Baror ,  William M. Johnson

发明人： Gigy Baror ,  William M. Johnson

IPC分类号： G06F12/08

CPC分类号： G06F12/0848

摘要： Methods and apparatus are disclosed for realizing an integrated cache unit (ICU) comprising both a cache memory and a cache controller on a single chip. The novel ICU is capable of being programmed, supports high speed data and instruction processing applications in both Reduced Instruction Set Computers (RISC) and non-RISC architecture environments, and supports high speed processing applications in both single and multiprocessor systems. The preferred ICU has two buses, one for the processor interface and the other for a memory interface. The ICU support single, burst and pipelined processor accesses and is capable of operating at frequencies in excess of 25 megahertz, achieving processor access times of two cycles for the first access in a sequence, and one cycle for burst mode or piplined accesses. It can be used as either an instruction or data cache with flexible internal cache organization. A RISC processor and two ICUs (for instruction and data cache) implements a very high performance processor with 16k bytes of cache. Larger caches can be designed by using additional ICUs which, according to the preferred embodiment of the invention, are modular. Further features include flexible and extensive multiprocessor support hardware, low power requirements, and support of a combination of bus watching, ownership schemes, software control and hardware control schemes which may be used with the novel ICU to achieve cache consistency.

摘要翻译： 公开了用于在单个芯片上实现包括高速缓冲存储器和高速缓存控制器的集成缓存单元（ICU）的方法和装置。 新型ICU能够被编程，支持精简指令集计算机（RISC）和非RISC架构环境中的高速数据和指令处理应用，并支持单处理器和多处理器系统中的高速处理应用。 优选的ICU有两条总线，一条用于处理器接口，另一条用于存储器接口。 ICU支持单个，突发和流水线处理器访问，并且能够在超过25兆赫的频率下工作，实现序列中第一次访问的两个周期的处理器访问时间，以及用于突发模式或直接访问的一个周期。 它可以用作具有灵活内部缓存组织的指令或数据缓存。 RISC处理器和两个ICU（用于指令和数据缓存）实现了一个非常高性能的处理器，具有16k字节的缓存。 可以通过使用附加的ICU来设计更大的高速缓存，根据本发明的优选实施例，它们是模块化的。 其他功能包括灵活且广泛的多处理器支持硬件，低功耗要求，以及支持总线监视，所有权方案，软件控制和硬件控制方案的组合，可与新型ICU一起使用以实现高速缓存的一致性。

公开(公告)号：US4851990A

公开(公告)日：1989-07-25

申请号：US12226

申请日：1987-02-09

申请人： William M. Johnson ,  Gigy Baror

发明人： William M. Johnson ,  Gigy Baror

IPC分类号： G06F13/16 ,  G06F9/32 ,  G06F12/06 ,  G06F13/18 ,  G06F13/42 ,  G06F15/78

CPC分类号： G06F13/4243 ,  G06F15/7835

摘要： Methods and apparatus for realizing a high performance interface between a processor, constituting part of a reduced instruction set computer (RISC) system, and a set of devices, including memory means. According to the invention, the interface includes three independent buses. A shared processor output bus, a processor input instruction bus, and a bidirectional data bus. The shared processor output address bus coupled the processor and the computer's memory. This bus carries both instructon and data access signals being transmitted by the processor to the memory. The processor input instruction bus also couples the processor and the computer's memory means, but carries instruction signals being transmitted from the memory to the processor. The bidirectional data bus provides a signal path for carrying data signals being transmitted by the memory to the processor and vice-a-versa. The novel interface uses demultiplexed buses for simpler timing and uses the separate data and instruction buses to provide extremely high transfer rates at a reasonable cost. The shared address bus accommodates pipelined and burst mode processor protocols with the burst mode protocol allowing concurrent data and instruction transfers. Methods and apparatus for controlling the buses and reporting bus status, etc., are also part of the invention and facilitate the implementation of features that include status reporting, handshaking between devices and the RISC processor, and bus arbitration.

公开(公告)号：US4761567A

公开(公告)日：1988-08-02

申请号：US52623

申请日：1987-05-20

申请人： Donald M. Walters, Jr. ,  Gigy Baror

发明人： Donald M. Walters, Jr. ,  Gigy Baror

IPC分类号： G11C11/407 ,  G06F1/04 ,  G06F1/06 ,  G06F1/10 ,  H03K5/00 ,  H03K19/096 ,  H03K3/66 ,  H03K5/15

CPC分类号： G06F1/06

摘要： An integrated circuit includes an input clock generator circuit responsive to an external TTL level clock signal for generating an internal CMOS level system clock signal for its own use and for use by other integrated circuits. The integrated circuit also includes an internal clock generator circuit responsive to either the internal CMOS level system clock signal or an external CMOS level system clock signal for generating internal CMOS level phase clock signals for its own use. As a result, the integrated circuit has a higher speed of operation since the propagation delay between the CMOS level system clock signal and internal clock signals has been minimized.

公开(公告)号：US06507899B1

公开(公告)日：2003-01-14

申请号：US09460534

申请日：1999-12-13

申请人： Klaus Oberlaender ,  Sabeen Randhawa ,  Yannick Martelloni ,  Manfred Henftling ,  Rami Zemach ,  Zohar Peleg ,  Christian Wiedholz ,  Gigy Baror ,  Doron Shoham ,  Oded Trainin ,  Niv Margalit

发明人： Klaus Oberlaender ,  Sabeen Randhawa ,  Yannick Martelloni ,  Manfred Henftling ,  Rami Zemach ,  Zohar Peleg ,  Christian Wiedholz ,  Gigy Baror ,  Doron Shoham ,  Oded Trainin ,  Niv Margalit

IPC分类号： G06F1208

CPC分类号： G06F12/0215

摘要： An interface circuit for coupling a data handling unit with a memory unit having control inputs, an address signal input, a data signal input, and a data signal output is described. The interface circuit comprises an address buffer having an input and an output, said input receiving an address signal from said data handling unit, a first multiplexer which couples said memory unit with either said output of said address buffer or with said address signal, a data buffer having an input and an output, said input receiving a data signal from said data handling unit and said output being coupled with said memory data input, a second multiplexer for selecting either said memory data signal output or said data buffer output, and a comparator for comparing said address signal with the signal from said address buffer output, generating a control signal which controls said second multiplexer.

摘要翻译： 描述了一种用于将数据处理单元与具有控制输入，地址信号输入，数据信号输入和数据信号输出的存储单元耦合的接口电路。 接口电路包括具有输入和输出的地址缓冲器，所述输入接收来自所述数据处理单元的地址信号，第一多路复用器将所述存储单元与所述地址缓冲器的所述输出或所述地址信号相耦合，数据 具有输入和输出的缓冲器，所述输入接收来自所述数据处理单元的数据信号，并且所述输出与所述存储器数据输入耦合;第二多路复用器，用于选择所述存储器数据信号输出或所述数据缓冲器输出;以及比较器 用于将所述地址信号与来自所述地址缓冲器输出的信号进行比较，产生控制所述第二多路复用器的控制信号。

公开(公告)号：US6014728A

公开(公告)日：2000-01-11

申请号：US785389

申请日：1997-01-21

申请人： Gigy Baror

发明人： Gigy Baror

IPC分类号： G06F12/08 ,  G06F12/10 ,  G06F12/00

CPC分类号： G06F12/0837 ,  G06F12/1027

摘要： A computer system having a cache memory subsystem which allows flexible setting of caching policies on a page basis and a line basis. A cache block status field is provided for each cache block to indicate the cache block's state, such as shared or exclusive. The cache block status field controls whether the cache control unit operates in a write-through write mode or in a copy-back write mode when a write hit access to the block occurs. The cache block status field may be updated by either a TLB write policy field contained within a translation look-aside buffer entry which corresponds to the page of the access, or by a second input independent of the TLB entry which may be provided from the system on a line basis.

摘要翻译： 一种具有高速缓冲存储器子系统的计算机系统，其允许以页面为基础和线基于灵活地设置高速缓存策略。 为每个高速缓存块提供高速缓存块状态字段以指示高速缓存块的状态，例如共享或排他。 高速缓存块状态字段控制当写入命中访问块时，高速缓存控制单元是以直写写入模式还是复制写入模式操作。 高速缓存块状态字段可以由包含在对应于访问的页面的转换后备缓冲器条目中的TLB写策略字段或独立于可从系统提供的TLB条目的第二输入来更新 在线的基础上