公开(公告)号：US5068823A

公开(公告)日：1991-11-26

申请号：US217616

申请日：1988-07-11

Applicant: Jeffrey I. Robinson

Inventor： Jeffrey I. Robinson

IPC: G06F15/177 ,  G06F15/78

CPC classification number: G06F15/7867 ,  G06F15/177 ,  G06F15/7835

Abstract: An apparatus architecture is provided which permits an easily programmed apparatus to serve as an equivalent of an integrated circuit chip, and/or as a building block for a large system. The apparatus is connected to a communications bus which receives apparatus parameter and topological information from a host processor and/or memory. The apparatus includes numerous functional blocks, a core, and a parametric bus. The functional blocks such as serial and parallel ports, D/A and A/D converters, biquad filters, etc. serve to process signal data and are connected in any desired manner through a switching matrix located in the core. The topology of the switching matrix is received via the communication bus. Parameters for the functional blocks are sent to the functional blocks via the communications bus, the core, and the parametric bus. Topological and/or parametric data may be burned into the switch matrix and functional blocks as permanent programmed memory, or held in programmable nonvolatile or volatile memory associated with the core and functional blocks. Signal data is typically received and transmitted via the serial and/or parallel ports and via the D/A and A/D converters (functional blocks) of the apparatus. The signal data is processed extremely quickly by having the parameterized functional blocks perform their operations on the signal data and by forwarding the results to another functional block via the topologically arranged switching matrix. Each apparatus can be made part of a larger wafer-scale system including several identical or architecturally similar apparatus by providing links between the cores of the apparatus.

Abstract translation: 提供了一种装置架构，其允许易编程的装置用作集成电路芯片的等同物，和/或用作大型系统的构建块。 该装置连接到从主处理器和/或存储器接收设备参数和拓扑信息的通信总线。 该装置包括许多功能块，核心和参数总线。 诸如串行和并行端口，D / A和A / D转换器，双二阶滤波器等功能块用于处理信号数据，并通过位于核心中的开关矩阵以任何期望的方式连接。 交换矩阵的拓扑通过通信总线接收。 功能块的参数通过通信总线，内核和参数总线发送到功能块。 拓扑和/或参数数据可以被刻录到开关矩阵和功能块中作为永久编程存储器，或者保存在与核心和功能块相关联的可编程非易失性或易失性存储器中。 信号数据通常经由串行和/或并行端口并经由设备的D / A和A / D转换器（功能块）来接收和发送。 通过使参数化的功能块对信号数据执行其操作并且经由拓扑布置的开关矩阵将结果转发到另一功能块，来极快地处理信号数据。 通过提供设备的核心之间的链接，每个装置可以被制成包括几个相同或结构上相似的装置的较大的晶片级系统的一部分。

公开(公告)号：US20230195682A1

公开(公告)日：2023-06-22

申请号：US18070514

申请日：2022-11-29

Applicant: Sunplus Technology Co., Ltd.

Inventor： Hsing-Sheng HUANG ,  Hao-Chang CHANG ,  Ming-Chang SU ,  Hwan-Rei LEE

IPC: G06F15/173 ,  G06F15/78 ,  G06F13/40

CPC classification number: G06F15/17306 ,  G06F15/7835 ,  G06F13/4027

Abstract: A chiplet system and a positioning method thereof are provided. The positioning method of the chiplet system includes the following steps. Two end chiplets and a plurality of middle chiplets are classified. A quantity calculation packet is transmitted and accumulated from each of the end chiplets towards another end to analyze a quantity of middle chiplets. A serial number comparison packet is transmitted and accumulated from each of the middle chiplets connected to one of the end chiplets towards another end to set a starting point. An identify number setting packet is transmitted and accumulated from the middle chiplet set as the starting point towards another end to set a positioning number of each of the middle chiplets.

公开(公告)号：US08004855B2

公开(公告)日：2011-08-23

申请号：US11481884

申请日：2006-07-07

Applicant: Yassir Salama ,  Assem Salama ,  Dennis Fitzgerald

Inventor： Yassir Salama ,  Assem Salama ,  Dennis Fitzgerald

IPC: H05K1/11

CPC classification number: H05K1/029 ,  G06F15/7835 ,  G06F15/7842 ,  H05K1/141 ,  H05K3/222 ,  H05K2201/10212 ,  H05K2201/10689

Abstract: A reconfigurable processing system is provided that comprises a plurality of programmable processing modules arranged on a circuit board. Each of the programmable processing modules is capable of being populated by a programmable integrated circuit of a variety of processing capabilities. Conductive traces on the circuit board connect to the programmable processing modules and the conductive traces are arranged on the circuit board so as to accommodate use of the programmable integrated circuits of varying processing capabilities in the programmable processing modules without the need to alter conductive trace footprints on the circuit board for the programmable processing modules. At least one interface circuit arranged on the circuit board to interface signals to and from the circuit board.

Abstract translation: 提供了一种可重构处理系统，其包括布置在电路板上的多个可编程处理模块。 每个可编程处理模块能够由各种处理能力的可编程集成电路填充。 电路板上的导电迹线连接到可编程处理模块，并且导电迹线布置在电路板上，以便适应在可编程处理模块中使用具有不同处理能力的可编程集成电路，而不需要改变导电迹线覆盖区 用于可编程处理模块的电路板。 布置在电路板上的至少一个接口电路，用于将信号与电路板接合。

公开(公告)号：US4086626A

公开(公告)日：1978-04-25

申请号：US693811

申请日：1976-06-07

Applicant: David H. Chung

Inventor： David H. Chung

IPC: G06F1/04 ,  G06F1/06 ,  G06F15/78 ,  G06F13/00

CPC classification number: G06F15/7835 ,  G06F1/04 ,  G06F1/06

Abstract: A microprocessor system having at least two separate scale integration devices. A first of the two large scale integration devices is a central processing unit formed on a single semiconductor die, and the second large scale integration device is a memory circuit formed on a separate single semiconductor die. The term "die" as used herein is conventional and refers to a unitary semiconductor body or chip. The central processing unit requires an external program counter which contains memory addresses of instruction codes to be used by the central processing unit. The memory device is electrically coupled to the central processing unit and includes a memory for storing the instruction codes, and a program counter for addressing the memory. Provision is made to incorporate additional memory circuits to expand the size and capability of the microprocessor system. System interrupt circuitry is also provided for interrupting system operation to change to a new sequence of instruction codes.

Abstract translation: 一种具有至少两个分开的规模集成装置的微处理器系统。 两个大规模集成装置中的第一个是形成在单个半导体管芯上的中央处理单元，第二大规模集成装置是形成在单独的半导体管芯上的存储电路。 本文所用的术语“裸片”是常规的，并且是指整体半导体本体或芯片。 中央处理单元需要外部程序计数器，其中包含中央处理单元要使用的指令代码的存储器地址。 存储器件电耦合到中央处理单元，并且包括用于存储指令代码的存储器和用于寻址存储器的程序计数器。 提供了额外的存储器电路以扩大微处理器系统的尺寸和能力。 还提供系统中断电路用于中断系统操作以改变为新的指令代码序列。

公开(公告)号：US08239539B2

公开(公告)日：2012-08-07

申请号：US12639360

申请日：2009-12-16

Applicant: Kenneth C. Duisenberg ,  Stephen B. Lyle ,  Rajeev Grover ,  Loren M. Koehler ,  Ivan Farkas

Inventor： Kenneth C. Duisenberg ,  Stephen B. Lyle ,  Rajeev Grover ,  Loren M. Koehler ,  Ivan Farkas

IPC: G06F13/00

CPC classification number: G06F15/7835 ,  G06F9/5077

Abstract: Systems, methods and computing components are provided for allocating a plurality of computing components among one or more logical partitions. Each of the plurality of computing components may have a management processor that is configured to assume a role among management processors of a partition. Each management processor may then cooperate with other management processors of the partition to control resources of the partition.

Abstract translation: 系统，方法和计算组件被提供用于在一个或多个逻辑分区之间分配多个计算组件。 多个计算组件中的每一个可以具有被配置为在分区的管理处理器中承担角色的管理处理器。 然后，每个管理处理器可以与分区的其他管理处理器协作来控制分区的资源。

公开(公告)号：US5590349A

公开(公告)日：1996-12-31

申请号：US900536

申请日：1992-06-18

Applicant: Jeffrey I. Robinson ,  Keith Rouse ,  Bruce R. Musicus

Inventor： Jeffrey I. Robinson ,  Keith Rouse ,  Bruce R. Musicus

IPC: G06F9/38 ,  G06F15/173 ,  G06F15/177 ,  G06F15/78

CPC classification number: G06F9/38 ,  G06F15/173 ,  G06F15/177 ,  G06F15/7835

Abstract: A programmable integrated signal processor ("SPROC") is provided having a multiported central memory unit (RAM), a program memory, at least one, and preferably a plurality of digital processors coupled to the multiported RAM and to the program memory, a data flow manager which controls external data flowing into the SPROC and processed data flowing out of the SPROC by acting as an interface of such data with the multiported RAM, input and output ports coupled to the DFM and acting as serial interfaces for the SPROC, and a host port permitting the programming of the SPROC and acting as a parallel interface to the SPROC. SPROCs may be coupled via the input and output ports to provide a system. The SPROC architecture permits the SPROC system to be computationally expandable, to have low latency and parasitic overhead for real time I/O, to efficiently execute a multiple of asynchronous processes, and to easily interface with microprocessors of various formats. The SPROC architecture in conjunction with a compiler and user interface system permits a user to "sketch and realize" complex circuits in the SPROC. An access port coupled to the multiported data RAM and the program RAM is provided for debugging purposes and permits reading and writing to data and program RAM memory locations. A probe permits monitoring of a memory location and provides an analog signal indicative thereof. The SPROC accomplishes for signal processing that which a microprocessor accomplishes for logic processing, and is further also easily realized in silicon.

Abstract translation: 提供了一种可编程集成信号处理器（“SPROC”），其具有多端口中央存储器单元（RAM），程序存储器，耦合到多端口RAM和程序存储器的至少一个，优选多个数字处理器，数据 流量管理器，其控制流入SPROC的外部数据，以及通过充当这样的数据与多端口RAM，连接到DFM的输入和输出端口并用作SPROC的串行接口的SPROC流出的处理数据，以及 主机端口允许对SPROC进行编程，并作为SPROC的并行接口。 SPROC可以经由输入和输出端口耦合以提供系统。 SPROC架构允许SPROC系统在计算上可扩展，对于实时I / O具有低延迟和寄生开销，有效地执行多个异步进程，并且可以轻松地与各种格式的微处理器进行接口。 SPROC架构与编译器和用户界面系统相结合，允许用户在SPROC中“绘制和实现”复杂的电路。 提供耦合到多端口数据RAM和程序RAM的访问端口用于调试目的，并允许读取和写入数据和程序RAM存储器位置。 探测器允许监视存储器位置并提供指示其的模拟信号。 SPROC完成了微处理器对逻辑处理完成的信号处理，并且还可以在硅中轻松实现。

公开(公告)号：US5263143A

公开(公告)日：1993-11-16

申请号：US34586

申请日：1993-03-22

Applicant: Jeffrey I. Robinson ,  Keith Rouse ,  Terry F. Montlick

Inventor： Jeffrey I. Robinson ,  Keith Rouse ,  Terry F. Montlick

IPC: G06F11/36 ,  G06F15/177 ,  G06F15/78 ,  G06F11/00

CPC classification number: G06F11/364 ,  G06F11/3648 ,  G06F15/177 ,  G06F15/7835

Abstract: A real time probe device is provided for a digital signal processor having a multiported data RAM, a time division multiplexed data RAM bus, and a processor. The probe includes a programmable comparator coupled to the address lines of the data RAM bus for determining that data is being written to a location of the multiported data RAM specified by the programmable comparator, a circuit for receiving the data on the data lines of the data RAM bus and for writing the data to a data buffer in the multiported data RAM, a reading circuit for obtaining the data from the data buffer of the multiported data RAM, and preferably a digital to analog converter for receiving at regular intervals the data obtained from the multiported data RAM and providing an analog signal therefrom. The average data rate at which data is written to the buffer in the data RAM should be the same as the rate at which data is obtained from the buffer of the data RAM for D/A conversion. Preferably, the buffer of the multiported data RAM into which the data is written and read by the probe is of variable length depending upon the RAM address to be probed. In this manner, delay is kept to a minimum.

Abstract translation: 为具有多端口数据RAM，时分复用数据RAM总线和处理器的数字信号处理器提供实时探针装置。 探头包括耦合到数据RAM总线的地址线的可编程比较器，用于确定数据正被写入由可编程比较器指定的多端口数据RAM的位置，用于接收数据的数据线上的数据的电路 RAM总线，并将数据写入多端口数据RAM中的数据缓冲器，读取电路，用于从多端口数据RAM的数据缓冲器获取数据，最好是一个数模转换器，用于定期接收从 多端口数据RAM并从其提供模拟信号。 将数据写入数据RAM中的缓冲器的平均数据速率应与从D / A转换的数据RAM的缓冲器获得数据的速率相同。 优选地，由探头写入和读取数据的多端口数据RAM的缓冲器的长度取决于要探测的RAM地址。 以这种方式，将延迟保持最小。

公开(公告)号：US3939452A

公开(公告)日：1976-02-17

申请号：US378354

申请日：1973-07-11

Applicant: Gian Franco Faggian

Inventor： Gian Franco Faggian

IPC: G06F9/22 ,  G06F1/12 ,  G06F1/22 ,  G06F9/30 ,  G06F15/02 ,  G06F15/78 ,  G06F15/20 ,  G06F9/06 ,  G06F9/16 ,  G06F13/00

CPC classification number: G06F1/22 ,  G06F1/12 ,  G06F15/7835

Abstract: A desk-top electronic computer with MOS circuit logic comprising an input device, an output device and a logic unit adapted to carry out the various operations of the computer. The logic unit is disposed on at least two MOS circuit chips synchronized by a main oscillator. Each MOS chip is provided with a corresponding timing circuit adapted to generate mutually coordinated timing signals. The logic unit includes a read only memory or ROM for storing the microinstructions commanding the various functions, a computing unit and a control unit adapted to permit the selection of the microinstructions from the ROM by addressed access for the purpose of supplying a sequence of microinstructions to the computing unit, access of the address and output of the microinstructions taking place through a single connection between the ROM and the control unit.

Abstract translation: 一种具有MOS电路逻辑的台式电子计算机，包括输入装置，输出装置和适于执行计算机的各种操作的逻辑单元。 逻辑单元设置在由主振荡器同步的至少两个MOS电路芯片上。 每个MOS芯片设置有适于产生相互协调的定时信号的相应的定时电路。 逻辑单元包括用于存储命令各种功能的微指令的只读存储器或ROM，计算单元和控制单元，该计算单元和控制单元适于通过寻址访问来从ROM中选择微指令，以将微指令序列提供给 计算单元，通过ROM和控制单元之间的单个连接进行地址的输入和微指令的输出。

公开(公告)号：US3745532A

公开(公告)日：1973-07-10

申请号：US3745532D

申请日：1970-05-27

Applicant: HUGHES AIRCRAFT CO

Inventor： ERWIN F

IPC: G06F9/26 ,  G06F9/28 ,  G06F15/78 ,  G06F13/00

CPC classification number: G06F9/262 ,  G06F9/28 ,  G06F15/7835

Abstract: Modular digital processing equipment of the type that can include one or more functional characters of the type that include an input bus, an output bus, control signal input means and which can have inputs and outputs that can be connected to similar or other characters for modular expansion of the operational capabilities. The functional characters including: a modular register character which provides storage for operands of a micro-program; a general logic character that performs basic logic functions for use by the micro-program; an arithmetic logic character that provides major arithmetic functions for use by the micro-program; an input/output character that provides input/output interface to the micro-program machine; a micromemory counter character that provides micromemory address registers and related functions; a micro-instruction register that contains the micromemory word registers; and a micro-array character that contains a micromemory array.

公开(公告)号：US11971844B2

公开(公告)日：2024-04-30

申请号：US18070514

申请日：2022-11-29

Applicant: Sunplus Technology Co., Ltd.

Inventor： Hsing-Sheng Huang ,  Hao-Chang Chang ,  Ming-Chang Su ,  Hwan-Rei Lee

IPC: G06F15/173 ,  G06F13/40 ,  G06F15/78

CPC classification number: G06F15/17306 ,  G06F13/4027 ,  G06F15/7835

Abstract: A chiplet system and a positioning method thereof are provided. The positioning method of the chiplet system includes the following steps. Two end chiplets and a plurality of middle chiplets are classified. A quantity calculation packet is transmitted and accumulated from each of the end chiplets towards another end to analyze a quantity of middle chiplets. A serial number comparison packet is transmitted and accumulated from each of the middle chiplets connected to one of the end chiplets towards another end to set a starting point. An identify number setting packet is transmitted and accumulated from the middle chiplet set as the starting point towards another end to set a positioning number of each of the middle chiplets.