公开(公告)号：US20050240793A1

公开(公告)日：2005-10-27

申请号：US10819241

申请日：2004-04-06

申请人： Kevin Safford ,  Donald Soltis

发明人： Kevin Safford ,  Donald Soltis

IPC分类号： G06F9/30 ,  G06F11/00

CPC分类号： G06F9/30181 ,  G06F9/30076 ,  G06F9/30189 ,  G06F9/3851 ,  G06F11/1629 ,  G06F2201/845

摘要： In one aspect of the present invention, a circuit is provided which implements an instruction set architecture defining a first instruction group, a second instruction group to enter a high-reliability mode of operation, and a third instruction group to enter a non-high-reliability mode of operation. The circuit includes means for causing the circuit to enter the high-reliability mode of operation in response to receiving the second instruction group; means for causing the circuit to enter the non-high-reliability mode of operation in response to receiving the third instruction group; first execution means for executing the first instruction group in the high-reliability mode of operation if the circuit is in the high-reliability mode of operation; and second execution means for executing the first instruction group without in the non-high-reliability mode of operation if the circuit is in the non-high-reliability mode of operation.

摘要翻译： 在本发明的一个方面，提供一种电路，其实现定义第一指令组的指令集架构，进入高可靠性操作模式的第二指令组，以及进入非高速模式的第三指令组， 可靠的运行模式。 电路包括用于响应于接收到第二指令组而使电路进入高可靠性操作模式的装置; 响应于接收到第三指令组使电路进入非高可靠性操作模式的装置; 如果电路处于高可靠性操作模式，则在高可靠性操作模式下执行第一指令组的第一执行装置; 以及第二执行装置，用于如果电路处于非高可靠性操作模式，则在不处于非高可靠性操作模式的情况下执行第一指令组。

公开(公告)号：US20050198538A1

公开(公告)日：2005-09-08

申请号：US10644184

申请日：2003-08-20

申请人： Donald Soltis ,  Glenn Colon-Bonet

发明人： Donald Soltis ,  Glenn Colon-Bonet

IPC分类号： G06F1/32 ,  G06F9/38 ,  G06F1/30

CPC分类号： G06F9/3867 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3243 ,  G06F9/3836 ,  G06F9/3857 ,  G06F9/3869 ,  Y02D10/126 ,  Y02D10/152

摘要： The invention controls maximum average power dissipation by stalling high power instructions through the pipeline of a pipelined processor. A power dissipation controller stalls the high power instructions in order to control the processor's maximum average power dissipation. Preferably, the controller is modeled after a capacitive system with a constant output rate and a throttled input rate: the output rate represents the steady state maximum average power dissipation; while the input rate is stalled based upon current capacity, representing thermal response time. At start-up, the capacity is initialized. Yet for each high power instruction, the capacity increases by a weighted value. Each clock capacity is also decreased by a variable output rate. In particular, a low power operation is inserted to the stage execution circuit where the stall is desired, creating a low power state for that circuit. This stall effectively creates a “hole” at that pipeline stage, thus temporarily reducing power dissipation. The invention takes advantage of the fact that the presence of an instruction at any stage execution circuit dissipates power and that the absence (i.e., a “hole”) of an instruction at any stage dissipates less power. By controlling where and when a hole occurs within the pipeline, the maximum average power dissipation of the processor is controlled.

摘要翻译： 本发明通过流水线处理器的流水线停止高功率指令来控制最大平均功耗。 功耗控制器停止高功率指令，以控制处理器的最大平均功耗。 优选地，控制器在具有恒定输出速率和节流输入速率的电容系统之后被建模：输出速率表示稳态最大平均功率耗散; 而输入速率则基于当前容量而停滞，代表热响应时间。 启动时，容量初始化。 然而对于每个大功率指令，容量增加一个加权值。 每个时钟容量也以可变输出速率降低。 特别地，低功率操作被插入到期望失速的级执行电路中，为该电路产生低功率状态。 这个停顿在该流水线阶段有效地创建了一个“孔”，从而暂时降低功耗。 本发明利用了在任何阶段执行电路中存在指令消耗功率并且任何阶段的指令的不存在（即，“孔”）消耗较少功率的事实。 通过控制在管道内发生孔的何处和何时，控制处理器的最大平均功耗。