Scanning circuit
    11.
    发明授权
    Scanning circuit 失效
    扫描电路

    公开(公告)号:US5510805A

    公开(公告)日:1996-04-23

    申请号:US453495

    申请日:1995-05-30

    申请人: Sywe N. Lee

    发明人: Sywe N. Lee

    IPC分类号: G09G3/36

    CPC分类号: G09G3/3677

    摘要: A row select driver circuit is used to energize each pixel row sequentially of a liquid crystal display. The output of each row select driver circuit is connected to a corresponding pixel row line and to a succeeding row select driver circuit as an activating input. All the row select driver circuits are integrated with thin-film transistors and deposited on the same glass substrate as the pixels. The number of leads connected to the assembly is much less than the number of pixel rows, including two sets of overlapping clock signals (three each for odd-numbered rows and even-numbered rows offset by one scanning line time) with different pulsewidths and periods twice as long as the scanning line time, a clock signal with a period as long as the scanning line time, a shift-in signal, a positive power supply terminal and at least one ground. These long clock periods precharge the following stage so as to effect a faster deselect time by overcoming the long time constant due to the high series of the thin-film transistors. In one example, the number of leads is reduced from 240 to 11.

    摘要翻译: 行选择驱动电路用于依次向液晶显示器供电。 每行选择驱动器电路的输出连接到对应的像素行线,并连接到作为激活输入的后续行选择驱动器电路。 所有行选择驱动电路与薄膜晶体管集成在一起,并与像素一起沉积在相同的玻璃基板上。 连接到组件的引线的数量远小于像素行的数量,包括两组重叠的时钟信号(三个用于奇数行和偶数行偏移一个扫描线时间),具有不同的脉冲宽度和周期 扫描线时间的两倍,具有与扫描线时间相同的周期的时钟信号,移入信号,正电源端子和至少一个接地。 这些长时钟周期为后续阶段预充电,以便通过克服由于薄膜晶体管的高系列而导致的长时间常数来实现更快的取消选择时间。 在一个示例中,引线的数量从240减少到11。

    Data driving circuit for LCD display
    12.
    发明授权
    Data driving circuit for LCD display 失效
    LCD显示数据驱动电路

    公开(公告)号:US5426447A

    公开(公告)日:1995-06-20

    申请号:US971721

    申请日:1992-11-03

    申请人: Sywe N. Lee

    发明人: Sywe N. Lee

    摘要: A data driver circuit and system driving scheme that can be integrated directly onto an LCD display substrate to eliminate the cost of the peripheral integrated circuits and the hybrid assembly needed by unscanned active matrix liquid crystal displays to connect them to the array. A demultiplexer circuit is deposited on the display for demultiplexing a group of Y columns of multiplexed video data input signals to X groups of Y pixel capacitors that are also deposited on the substrate in Z rows. In addition, a precharging circuit is deposited on the substrate to precharge the pixel capacitors to a first voltage level such that the video data input signals coupled thereto in a demultiplexed fashion causes the pixels to discharge to a second predetermined voltage level to provide a video display as the rows of pixels are sequentially scanned.

    摘要翻译: 数据驱动器电路和系统驱动方案,其可以直接集成到LCD显示器基板上,以消除未扫描有源矩阵液晶显示器所需的外围集成电路和混合组件的成本,以将它们连接到阵列。 解复用器电路沉积在显示器上,用于将多路复用的视频数据输入信号的一列Y列解复用于也在Z行中沉积在衬底上的X组Y像素电容器。 此外,预充电电路沉积在衬底上以将像素电容器预充电到第一电压电平,使得以解复用方式耦合到其上的视频数据输入信号使得像素放电到第二预定电压电平以提供视频显示 因为像素行被依次扫描。

    Select driver circuit for an LCD display
    13.
    发明授权
    Select driver circuit for an LCD display 失效
    选择LCD显示器的驱动电路

    公开(公告)号:US5313222A

    公开(公告)日:1994-05-17

    申请号:US996979

    申请日:1992-12-24

    申请人: Sywe N. Lee

    发明人: Sywe N. Lee

    IPC分类号: G02F1/133 G09G3/36

    CPC分类号: G09G3/3677

    摘要: A circuit for use with an LCD display wherein the LCD display contains a first number of pixel columns and a second number of pixel rows on a substrate is provided. The circuit comprises a plurality of row select driver circuits corresponding to the number of pixel rows for electrically energizing the pixel rows. The row select driver circuit is deposited on the LCD display substrate and an output of each of the row select driver circuits is electrically connected to a corresponding pixel row and to a successive row select driver circuit as an activating input. Switching apparatus external to the LCD display and having leads electrically connected to the row select driver circuits is also provided for electrically switching the row select driver circuits such that each pixel row is sequentially energized. A corresponding method is also disclosed.

    摘要翻译: 一种用于LCD显示器的电路,其中LCD显示器包含第一数量的像素列和在基板上的第二数量的像素行。 该电路包括多个行选择驱动器电路,其对应于用于电激励像素行的像素行数。 行选择驱动器电路沉积在LCD显示基板上,并且每个行选择驱动电路的输出电连接到对应的像素行和连续的行选择驱动器电路作为激活输入。 还提供了LCD显示器外部并具有电连接到行选择驱动器电路的引线的开关装置,用于电行切换行选择驱动器电路,使得每个像素行被依次通电。 还公开了相应的方法。

    Interlace overlap pixel design for high sensitivity CMOS image sensors
    14.
    发明授权
    Interlace overlap pixel design for high sensitivity CMOS image sensors 失效
    交错重叠像素设计用于高灵敏度CMOS图像传感器

    公开(公告)号:US06867806B1

    公开(公告)日:2005-03-15

    申请号:US09433677

    申请日:1999-11-04

    摘要: In a CMOS-type image sensor, a plurality of pairs of light-detecting elements (LDEs) are arranged in rows and columns to generate analog signals proportional to the intensity of light impinging on respective one of the LDEs. First and second photo sensing means in each pair of LDEs are coupled in parallel, in the column direction, at a floating sensing point through first turn-on means. The first and second photo sensing means in adjacent pairs of LDEs are coupled in parallel in the column direction through second turn-on means. The first turn-on means are enabled by first control lines and the second turn-on means are enabled by second control lines coupled thereto, respectively. Analog signals acquired in the first and second photo sensing means of one pair or of adjacent pairs are present at the floating sensing point in response to the enabling of the first or second control lines, respectively.

    摘要翻译: 在CMOS型图像传感器中,多对光检测元件(LDE)以行和列布置,以产生与照射在相应的一个LDE上的光的强度成比例的模拟信号。 每对LDE中的第一和第二感光装置在列方向上通过第一导通装置在浮动感测点处并联耦合。 相邻的LDE对中的第一和第二光感测装置通过第二导通装置在列方向上并联耦合。 第一接通装置由第一控制线使能,第二接通装置分别由与其耦合的第二控制线启用。 响应于第一或第二控制线的使能,在浮动感测点处存在在一对或相邻对的第一和第二光感测装置中获取的模拟信号。

    Sample and hold circuit for drivers of an active matrix display
    15.
    发明授权
    Sample and hold circuit for drivers of an active matrix display 失效
    有源矩阵显示驱动器采样和保持电路

    公开(公告)号:US5903250A

    公开(公告)日:1999-05-11

    申请号:US731644

    申请日:1996-10-17

    IPC分类号: G09G3/36

    CPC分类号: G09G3/3688

    摘要: The number of external column driver chip can be reduced to one in an active matrix liquid crystal display with column input multiplexing driving scheme. At least two sample and hold circuits are used for each column with alternate sampling and holding periods. Video signals are sampled and held at least twice during one line scanning time. These sample and hold circuits are all integrated in the driver chip.

    摘要翻译: 在列输入多路复用驱动方案的有源矩阵液晶显示器中,外部列驱动芯片的数量可以减少到一个。 每个列使用至少两个采样和保持电路,具有交替的采样和保持周期。 在一行扫描时间期间,视频信号被采样并保持至少两次。 这些采样和保持电路都集成在驱动器芯片中。

    CMOS level shifter circuit
    16.
    发明授权
    CMOS level shifter circuit 失效
    CMOS电平移位电路

    公开(公告)号:US5113097A

    公开(公告)日:1992-05-12

    申请号:US696981

    申请日:1991-05-02

    申请人: Sywe N. Lee

    发明人: Sywe N. Lee

    IPC分类号: H03K19/0185

    CPC分类号: H03K19/018521

    摘要: A level shifter circuit has a pair of voltage buses, first and second p-channel MOS transistors and third and fourth n-channel MOS transistors. Each transistor has a gate to control conduction. The first and third transistors are connected in series between the voltage buses and the second and fourth transistors are connected in series between the voltage buses. A node between the first and second transistors is connected to the gates of the second and fourth transistors. An input signal having one of first and second levels is applied to the gate of the first transistor while the inverse of the input signal is applied to the gate of the second transistor. One voltage bus is connected through one of the second and fourth transistors in response to the first level input signal. The other voltage bus is connected the other of the second and fourth transistors in response to the second level input signal.

    摘要翻译: 电平移位器电路具有一对电压总线,第一和第二p沟道MOS晶体管以及第三和第四n沟道MOS晶体管。 每个晶体管都有一个栅极来控制导通。 第一和第三晶体管串联连接在电压总线之间,第二和第四晶体管串联连接在电压总线之间。 第一和第二晶体管之间的节点连接到第二和第四晶体管的栅极。 具有第一和第二电平之一的输入信号被施加到第一晶体管的栅极,而输入信号的反相被施加到第二晶体管的栅极。 响应于第一电平输入信号,一个电压总线通过第二和第四晶体管之一连接。 响应于第二电平输入信号,另一个电压总线连接第二和第四晶体管中的另一个。