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公开(公告)号:US20190179397A1
公开(公告)日:2019-06-13
申请号:US16165878
申请日:2018-10-19
Inventor: Sukho LEE , Jae-Jin LEE , Kyuseung HAN
Abstract: Provided is a graphics processing unit and an operation method thereof. The graphics processing unit includes a plurality of cores in which a delay time between an input and an output decreases according to an increase of a temperature, a temperature monitoring and sorting circuit configured to monitor a temperature of each of the plurality of cores, and a controller configured to control a clock frequency and a power supply of the plurality of cores based on a drivable clock frequency of a core having the lowest temperature among temperatures of each of the plurality of monitored cores.
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公开(公告)号:US20180109415A1
公开(公告)日:2018-04-19
申请号:US15644434
申请日:2017-07-07
Inventor: Kyuseung HAN , Woojoo LEE , Jae-Jin LEE , Sung Weon KANG
IPC: H04L12/24 , H03K17/14 , H04L12/933
CPC classification number: H04L41/0803 , H01L29/785 , H03K17/145 , H03K19/0016 , H03K19/00384 , H04L41/0672 , H04L43/08 , H04L49/101
Abstract: Provided is a network-on-chip (NoC). The NoC includes a plurality of routers configured to receive power through each corresponding power gating switch, and a controller configured to control a power gating switch of each of the plurality of routers based on temperature information provided from each of the plurality of routers and control a driving clock of the plurality of routers. The controller controls the power gating switch to turn off at least one first router by referring to the temperature information and over-scale a clock frequency of at least one turned-on second router.
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