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公开(公告)号:US10817783B1
公开(公告)日:2020-10-27
申请号:US16868936
申请日:2020-05-07
Applicant: Facebook, Inc.
Inventor: Nadav Rotem , Abdulkadir Utku Diril , Mikhail Smelyanskiy , Jong Soo Park , Christopher Dewan
Abstract: The disclosed computer-implemented method for efficiently updating neural networks may include (i) identifying a neural network that comprises sets of interconnected nodes represented at least in part by a plurality of matrices and that is trained on a training computing device and executes on at least one endpoint device, (ii) constraining a training session for the neural network to reduce the size in memory of the difference between the previous values of the matrices prior to the training session and the new values of the matrices after the training session, (iii) creating a delta update for the neural network that describes the difference between the previous values and the new values, and (iv) updating the neural network on the endpoint device to the new state by sending the delta update from the training computing device to the endpoint computing device. Various other methods, systems, and computer-readable media are also disclosed.
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公开(公告)号:US20200160848A1
公开(公告)日:2020-05-21
申请号:US16749328
申请日:2020-01-22
Applicant: Facebook, Inc.
Inventor: Nadav Rotem , Abdulkadir Utku Diril , Mikhail Smelyanskiy , Jong Soo Park , James Kenneth Reed
Abstract: The disclosed method may include (1) determining whether a next operation of a plurality of operations of an artificial neural network (ANN) is dependent upon a Boolean predication value based on a representative value for a weight or an input of a node of the ANN, (2) based on the next operation not being dependent on the Boolean predication value, allowing the next operation to update a state of the ANN, and (3) based on the next operation being dependent on the Boolean predication value, performing at least one of (a) allowing, based on the Boolean predication value being a first value, the next operation to update the state of the ANN, and (b) preventing, based on the Boolean predication value being a second value different from the first value, the next operation from updating the state of the ANN. Various other methods and systems are also disclosed.
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公开(公告)号:US10474430B2
公开(公告)日:2019-11-12
申请号:US15857998
申请日:2017-12-29
Applicant: Facebook, Inc.
Inventor: Abdulkadir Utku Diril , Mikhail Smelyanskiy , Nadav Rotem , Jong Soo Park
Abstract: The disclosed method may include (1) receiving a precision level of each weight associated with each input of a node of a computational model, (2) identifying, for each weight, one of a plurality of multiplier groups, where each multiplier group may include a plurality of hardware multipliers of a corresponding bit width, and where the corresponding bit width of the plurality of hardware multipliers of the one of the plurality of multiplier groups may be sufficient to multiply the weight by the associated input, and (3) multiplying each weight by its associated input using an available hardware multiplier of the one of the plurality of multiplier groups identified for the weight. Various other processing elements, methods, and systems are also disclosed.
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公开(公告)号:US20190206390A1
公开(公告)日:2019-07-04
申请号:US15857990
申请日:2017-12-29
Applicant: Facebook, Inc.
Inventor: Nadav Rotem , Abdulkadir Utku Diril , Mikhail Smelyanskiy , Jong Soo Park , James Kenneth Reed
Abstract: The disclosed method may include (1) determining whether a next operation of a plurality of operations of a computational model is dependent upon a Boolean predication value, (2) based on the next operation not being dependent on the Boolean predication value, performing the next operation, where a state of the computational model is updated as a result of performing the next operation, and (3) based on the next operation being dependent on the Boolean predication value, performing at least one of (a) allowing, based on the Boolean predication value being a first value, the next operation to update the state of the computational model, and (b) preventing, based on the Boolean predication value being a second value different from the first value, the next operation from updating the state of the computational model. Various other methods and systems are also disclosed.
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公开(公告)号:US20210256363A1
公开(公告)日:2021-08-19
申请号:US16793961
申请日:2020-02-18
Applicant: Facebook, Inc.
Inventor: Krishnakumar Narayanan Nair , Rakesh Komuravelli , Abdulkadir Utku Diril , Ehsan Khish Ardestani Zadeh , Yuchen Hao , Martin Schatz , Thomas Mark Ulrich , Olivia Wu , Anup Ramesh Kadkol , Amin Firoozshahian
Abstract: A processor system comprises a first and second group of registers and a hardware channel convolution processor unit. The first group of registers is configured to store data elements of channels of a portion of a convolution data matrix. Each register stores at least one data element from each channel. The second group of registers is configured to store data elements of convolution weight matrices including a separate convolution weight matrix for each channel. Each register stores at least one data element from each convolution weight matrix. The hardware channel convolution processor unit is configured to multiply each data element in the first group of registers with a corresponding data element in the second group of registers and sum together the multiplication results for each specific channel to determine corresponding channel convolution result data elements in a corresponding channel convolution result matrix.
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公开(公告)号:US20210181957A1
公开(公告)日:2021-06-17
申请号:US16712253
申请日:2019-12-12
Applicant: Facebook, Inc.
Inventor: Abdulkadir Utku Diril , Olivia Wu , Krishnakumar Narayanan Nair , Aravind Kalaiah , Anup Ramesh Kadkol , Pankaj Kansal
Abstract: A system comprises a processor and a plurality of memory units. The processor is coupled to each of the plurality of memory units by a plurality of network connections. The processor includes a plurality of processing elements arranged in a two-dimensional array and a corresponding two-dimensional communication network communicatively connecting each of the plurality of processing elements to other processing elements on same axes of the two-dimensional array. Each processing element that is located along a diagonal of the two-dimensional array is configured as a request broadcasting master for a respective group of processing elements located along a same axis of the two-dimensional array.
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17.
公开(公告)号:US10948966B1
公开(公告)日:2021-03-16
申请号:US15914362
申请日:2018-03-07
Applicant: Facebook, Inc.
Inventor: Nadav Rotem , Abdulkadir Utku Diril , Mikhail Smelyanskiy , Jong Soo Park
IPC: G06F1/32 , G06F1/3234
Abstract: The disclosed computer-implemented method may include (i) identifying an artificial neural network that processes each input to the artificial neural network in a fixed number of operations, (ii) performing an analysis on the artificial neural network to determine an execution metric that represents the fixed number of operations performed by the artificial neural network to process each input, (iii) determining a quality-of-service metric for an executing system that executes the artificial neural network, and (iv) optimizing power consumption of the executing system by configuring, based on the execution metric and the quality-of-service metric, a processing throughput of at least one physical processor of the executing system, thereby causing the executing system to execute the artificial neural network at a rate that satisfies the quality-of-service metric while limiting the power consumption of the executing system. Various other methods, systems, and computer-readable media are also disclosed.
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公开(公告)号:US20210049229A1
公开(公告)日:2021-02-18
申请号:US16543241
申请日:2019-08-16
Applicant: Facebook, Inc.
Inventor: Krishnakumar Nair , Abdulkadir Utku Diril , Dheevatsa Mudigere , Olivia Wu , Ehsan Khish Ardestani Zadeh , Yuchen Hao
Abstract: A system comprises a matrix processor unit that includes a first type of register, a group of a second type of registers, and a plurality of calculation units. The first type of register is configured to concurrently store values from different rows of a first matrix. At least a portion of the first type of register is logically divided into groups of elements, and each of the groups corresponds to a different row of the first matrix. Each of the second type of registers is configured to concurrently store values from a plurality of different rows of a second matrix. Each of the calculation units corresponds to one of the second type of registers and is configured to at least in part determine a corresponding element in a result matrix of convoluting the second matrix with the first matrix.
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公开(公告)号:US10671147B2
公开(公告)日:2020-06-02
申请号:US15846117
申请日:2017-12-18
Applicant: Facebook, Inc.
Inventor: Nadav Rotem , Jong Soo Park , Mikhail Smelyanskiy , Abdulkadir Utku Diril
IPC: G06F1/00 , G06F1/3287 , G06F1/3228 , G06F9/38 , G06N5/02
Abstract: A computer-implemented method for dynamically managing the power usage and/or performance of an artificial intelligence (AI) hardware accelerator may include (1) receiving an instruction stream that includes one or more instructions for performing at least one AI-specific computing task, (2) identifying a plurality of special-purpose, hardware-based functional units configured to perform AI-specific computing tasks, (3) predicting, based on an analysis of at least a portion of the instruction stream, a power-usage requirement for at least one of the functional units when executing the instruction stream, and then (4) modifying, based on the power-usage requirement, the power supplied to at least one of the functional units. Various other methods and systems are also disclosed.
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公开(公告)号:US20190205358A1
公开(公告)日:2019-07-04
申请号:US15857918
申请日:2017-12-29
Applicant: Facebook, Inc.
Inventor: Abdulkadir Utku Diril , Jong Soo Park , Nadav Rotem , Mikhail Smelyanskiy
CPC classification number: G06F17/16 , G06F7/5443 , G06N3/0481 , G06N3/063
Abstract: A special-purpose, hardware-based accelerator may include an input subsystem configured to receive first and second vectors as operands of a full dot-product operation. The accelerator may also include a sparsity-aware dot-product engine communicatively coupled to the input subsystem and configured to perform adaptive dot-product processing by: (1) identifying, within the first and second vectors, at least one zero-value element and (2) executing, in response to identifying the zero-value element, a reduced dot-product operation that excludes, relative to the full dot-product operation, at least one mathematical operation in which the zero-value element is an operand. The accelerator may also include an output subsystem that is communicatively coupled to the sparsity-aware dot-product engine and configured to send a result of the reduced dot-product operation to a storage subsystem. Various other accelerators, computing systems, and methods are also disclosed.
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