公开(公告)号：US20150325681A1

公开(公告)日：2015-11-12

申请号：US14270824

申请日：2014-05-06

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Bongki Lee ,  Jin Ping Liu ,  Bharat Krishnan

IPC: H01L29/66

CPC classification number: H01L21/823842 ,  H01L21/32133 ,  H01L29/4966 ,  H01L29/66 ,  H01L29/66477

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method is provided for fabricating an integrated circuit. The method includes forming a first FET trench in a first FET region and a second FET trench in a second FET region of an interlayer dielectric material on a semiconductor substrate, at least partially filling the first and second FET trenches with a work function metal to form a work function metal layer, and at least partially removing a portion of the work function metal layer in the second FET trench. The first FET trench is defined as an NFET trench and the second FET trench is defined as a PFET trench.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个实施例中，提供了一种用于制造集成电路的方法。 该方法包括在半导体衬底上的层间电介质材料的第二FET区域中的第一FET区域和第二FET沟槽中形成第一FET沟槽，至少部分地用功函数金属填充第一和第二FET沟槽以形成 功函数金属层，并且至少部分去除第二FET沟槽中的功函数金属层的一部分。 第一FET沟槽被定义为NFET沟槽，并且第二FET沟槽被定义为PFET沟槽。

公开(公告)号：US20150294915A1

公开(公告)日：2015-10-15

申请号：US14749245

申请日：2015-06-24

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Jinping Liu ,  Bharat Krishnan ,  Bongki Lee ,  Vidmantas Sargunas ,  Weihua Tong ,  Seung Kim

IPC: H01L21/8238

CPC classification number: H01L21/823821 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785

Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming a first fin structure overlying a first type region in a semiconductor substrate and forming a second fin structure overlying a second type region in the semiconductor substrate. A gate is formed overlying each fin structure and defines a channel region in each fin structure. The method includes masking the second type region and etching the first fin structure around the gate in the first fin structure to expose the channel region in the first fin structure. Further, the method includes doping the channel region in the first fin structure, and forming source/drain regions of the first fin structure around the channel region in the first fin structure.

Abstract translation: 提供了制造集成电路的方法。 在一个实施例中，一种用于制造集成电路的方法包括：形成覆盖半导体衬底中的第一类型区域的第一鳍结构，并形成覆盖半导体衬底中第二类型区域的第二鳍结构。 形成在每个鳍结构上方的栅极，并且限定每个鳍结构中的沟道区。 该方法包括掩蔽第二类型区域并蚀刻第一鳍结构中的栅极周围的第一鳍结构以暴露第一鳍结构中的沟道区。 此外，该方法包括在第一鳍结构中掺杂沟道区，并且在第一鳍结构中的沟道区周围形成第一鳍结构的源/漏区。

公开(公告)号：US08912085B1

公开(公告)日：2014-12-16

申请号：US14017409

申请日：2013-09-04

Applicant: GlobalFoundries Inc.

Inventor： Bongki Lee ,  Bharat V. Krishnan ,  Jinping Liu

IPC: H01L21/3205 ,  H01L21/02 ,  H01L29/49 ,  H01L21/283 ,  H01L21/8238

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/823842 ,  H01L29/513

Abstract: A methodology for enabling a gate stack integration process that provides additional threshold voltage margin without sacrificing gate reliability and the resulting device are disclosed. Embodiments include conformally forming a margin adjusting layer in a gate trench, forming a metal capping layer on the margin adjusting layer, and forming an n-type work function (nWF) metal layer on the metal capping layer.

Abstract translation: 公开了一种能够提供附加阈值电压裕度而不牺牲门可靠性的门堆栈集成过程和所得到的器件的方法。 实施例包括在栅极沟槽中保形地形成边缘调整层，在边缘调整层上形成金属覆盖层，并在金属覆盖层上形成n型功函数（nWF）金属层。