公开(公告)号：US20240304724A1

公开(公告)日：2024-09-12

申请号：US18662615

申请日：2024-05-13

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shahaji B. MORE ,  Huai-Tei Yang ,  Shih-Chieh Chang ,  Cheng-Han Lee

IPC分类号： H01L29/78 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/66

CPC分类号： H01L29/7848 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823864 ,  H01L27/0924 ,  H01L29/167 ,  H01L29/66803 ,  H01L29/161 ,  H01L29/165

摘要： The present disclosure describes a method to form silicon germanium (SiGe) source/drain epitaxial stacks with a boron doping profile and a germanium concentration that can induce external stress to a fully strained SiGe channel. The method includes forming one or more gate structures over a fin, where the fin includes a fin height, a first sidewall, and a second sidewall opposite to the first sidewall. The method also includes forming a first spacer on the first sidewall of the fin and a second spacer on the second sidewall of the fin; etching the fin to reduce the fin height between the one or more gate structures; and etching the first spacer and the second spacer between the one or more gate structures so that the etched first spacer is shorter than the etched second spacer and the first and second etched spacers are shorter than the etched fin. The method further includes forming an epitaxial stack on the etched fin between the one or more gate structures.

公开(公告)号：US11935933B2

公开(公告)日：2024-03-19

申请号：US18131336

申请日：2023-04-05

申请人： Intel Corporation

发明人： Patrick Morrow ,  Rishabh Mehandru ,  Aaron D. Lilak ,  Kimin Jun

IPC分类号： H01L27/12 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L21/225 ,  H01L21/265

CPC分类号： H01L29/41791 ,  H01L21/823431 ,  H01L27/1266 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/4236 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/78 ,  H01L29/785 ,  H01L21/2254 ,  H01L21/26513 ,  H01L29/66545

摘要： An apparatus including a circuit structure including a device stratum including a plurality of devices including a first side and an opposite second side; and a metal interconnect coupled to at least one of the plurality of devices from the second side of the device stratum. A method including forming a transistor device including a channel between a source region and a drain region and a gate electrode on the channel defining a first side of the device; and forming an interconnect to one of the source region and the drain region from a second side of the device.

公开(公告)号：US20240014324A1

公开(公告)日：2024-01-11

申请号：US17810846

申请日：2022-07-06

申请人： NXP B.V.

发明人： Viet Thanh Dinh ,  Asanga H. Perera ,  Arjan Mels

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/84

CPC分类号： H01L29/7856 ,  H01L29/66803 ,  H01L27/0886 ,  H01L21/823431 ,  H01L21/845

摘要： A semiconductor device and methods of forming the same include a semiconductive fin protruding vertically from a body region and extending along a first direction, an insulator material above the body region and surrounding a lower portion of the fin, and a gap region between first and second ends of the semiconductive fin where at least a top portion of the semiconductive fin is absent. The device includes current terminals coupled to first and second ends of the fin, and a gate electrode and a gate extension coupled to the fin. The gate electrode surrounds the top portion of the semiconductive fin and is separated from the semiconductive by a gate insulator material. The gate extension has a first end adjacent to the gate electrode and a second end above the body region within the gap region.

公开(公告)号：US20230420246A1

公开(公告)日：2023-12-28

申请号：US17847625

申请日：2022-06-23

申请人： Intel Corporation

发明人： Ilya V. Karpov ,  Aaron A. Budrevich ,  Gilbert Dewey ,  Matthew V. Metz ,  Jack T. Kavalieros ,  Dan S. Lavric

IPC分类号： H01L21/02 ,  H01L21/24 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/02266 ,  H01L29/785 ,  H01L29/66803 ,  H01L21/24

摘要： An integrated circuit structure includes a source or drain region, and a contact coupled to the source or drain region. A region including metals and semiconductor materials is between the source or drain region and the contact. A first dopant is within the source or drain region, and a second dopants is within the region. In one example, the first dopant is elementally different from the second dopant. In another example, the first dopant is elementally same as the second dopant, wherein a concentration of the first dopant within a section of the source or drain region is within 20% of a concentration of the second dopant within the region, and wherein the section of the source or drain region is at a distance of at most 5 nanometers (nm) from the region.

公开(公告)号：US11855089B2

公开(公告)日：2023-12-26

申请号：US17835448

申请日：2022-06-08

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yong-Yan Lu ,  Chia-Wei Soong ,  Hou-Yu Chen

IPC分类号： H01L27/092 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/10 ,  H01L21/225 ,  H01L29/06

CPC分类号： H01L27/0921 ,  H01L21/2255 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785 ,  H01L29/7849

摘要： A semiconductor device includes a silicon substrate; a semiconductor fin over the silicon substrate; and an isolation structure over the silicon substrate. The semiconductor fin includes a first portion and a second portion over the first portion. The first portion is surrounded by the isolation structure, and the second portion protrudes above the isolation structure. The second portion has a different crystalline lattice constant than the first portion. The first portion includes a first dopant, and the second portion is substantially free of the first dopant. The semiconductor device further includes a gate structure above the isolation structure and engaging multiple surfaces of the second portion.

公开(公告)号：US20230223406A1

公开(公告)日：2023-07-13

申请号：US18185728

申请日：2023-03-17

申请人： Tahoe Research, Ltd.

发明人： Tahir GHANI ,  Salman Latif ,  Chanaka D. Munasinghe

IPC分类号： H01L27/092 ,  H01L27/088 ,  H01L21/225 ,  H01L29/08 ,  H01L21/8238 ,  H01L21/3105 ,  H01L21/265 ,  H01L21/8234 ,  H01L29/66

CPC分类号： H01L27/0924 ,  H01L21/2255 ,  H01L21/26513 ,  H01L21/31051 ,  H01L21/823431 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/66803

摘要： Non-planar semiconductor devices having doped sub-fin regions and methods of fabricating non-planar semiconductor devices having doped sub-fin regions are described. For example, a method of fabricating a semiconductor structure involves forming a plurality of semiconductor fins above a semiconductor substrate. A solid state dopant source layer is formed above the semiconductor substrate, conformal with the plurality of semiconductor fins. A dielectric layer is formed above the solid state dopant source layer. The dielectric layer and the solid state dopant source layer are recessed to approximately a same level below a top surface of the plurality of semiconductor fins, exposing protruding portions of each of the plurality of semiconductor fins above sub-fin regions of each of the plurality of semiconductor fins. The method also involves driving dopants from the solid state dopant source layer into the sub-fin regions of each of the plurality of semiconductor fins.

公开(公告)号：US20230215949A1

公开(公告)日：2023-07-06

申请号：US17569846

申请日：2022-01-06

申请人： International Business Machines Corporation

发明人： Chen Zhang ,  Junli Wang ,  Ruilong Xie ,  Dechao Guo ,  Sung Dae Suk

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L27/088 ,  H01L21/8234

CPC分类号： H01L29/7855 ,  H01L29/66803 ,  H01L29/66818 ,  H01L27/0886 ,  H01L21/823431

摘要： A semiconductor device includes a FinFET fin. The same FinFET fin is associated with a bottom FinFET and a top FinFET. The FinFET fin includes a lower channel portion, associated with the bottom FinFET, a top channel portion, associated with the top FinFET, and a channel isolator between the bottom channel portion and the top channel portion. A lower gate includes a vertical portion that is upon a sidewall of the bottom channel portion. An isolation layer may be formed upon the lower gate if it is desired for the top FinFET fin and the bottom FinFET fin to not share a gate. An upper gate is upon the top channel portion and is further upon the isolation layer, if present, or is upon the lower gate.

公开(公告)号：US20230197720A1

公开(公告)日：2023-06-22

申请号：US18171914

申请日：2023-02-21

申请人： Bell Semiconductor, LLC

发明人： Qing LIU ,  Prasanna KHARE ,  Nicolas LOUBET

IPC分类号： H01L27/088 ,  H01L21/84 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L21/265 ,  H01L29/417 ,  H01L21/8238 ,  H01L21/225 ,  H01L21/8234

CPC分类号： H01L27/0886 ,  H01L21/845 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/0847 ,  H01L21/26506 ,  H01L21/2658 ,  H01L21/26586 ,  H01L29/41783 ,  H01L21/823821 ,  H01L29/66803 ,  H01L21/2253 ,  H01L21/26513 ,  H01L21/823418 ,  H01L21/823431 ,  H01L29/41791

摘要： A multi-fin FINFET device may include a substrate and a plurality of semiconductor fins extending upwardly from the substrate and being spaced apart along the substrate. Each semiconductor fin may have opposing first and second ends and a medial portion therebetween, and outermost fins of the plurality of semiconductor fins may comprise an epitaxial growth barrier on outside surfaces thereof. The FIN FET may further include at least one gate overlying the medial portions of the semiconductor fins, a plurality of raised epitaxial semiconductor source regions between the semiconductor fins adjacent the first ends thereof, and a plurality of raised epitaxial semiconductor drain regions between the semiconductor fins adjacent the second ends thereof.

公开(公告)号：US11664452B2

公开(公告)日：2023-05-30

申请号：US17085981

申请日：2020-10-30

申请人： Intel Corporation

发明人： Pratik A. Patel ,  Mark Y. Liu ,  Jami A. Wiedemer ,  Paul A. Packan

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L21/225 ,  H01L21/324 ,  H01L29/08 ,  H01L29/24 ,  H01L29/267

CPC分类号： H01L29/7848 ,  H01L21/2253 ,  H01L21/324 ,  H01L29/0847 ,  H01L29/24 ,  H01L29/267 ,  H01L29/66492 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785 ,  H01L29/7851

摘要： A method including forming an opening in a junction region of a fin on and extending from a substrate; introducing a doped semiconductor material in the opening; and thermal processing the doped semiconductor material. A method including forming a gate electrode on a fin extending from a substrate; forming openings in the fin adjacent opposite sides of the gate electrode; introducing a doped semiconductor material in the openings; and thermally processing the doped semiconductor material sufficient to induce the diffusion of a dopant in the doped semiconductor material. An apparatus including a gate electrode transversing a fin extending from a substrate; and semiconductor material filled openings in junction regions of the fin adjacent opposite sides of the gate electrode, wherein the semiconductor material comprises a dopant.

公开(公告)号：US20190252527A1

公开(公告)日：2019-08-15

申请号：US16396961

申请日：2019-04-29

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Sai-Hooi Yeong ,  Sheng-Chen Wang ,  Bo-Yu Lai ,  Ziwei Fang ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC分类号： H01L29/66 ,  H01L21/265 ,  H01L29/165 ,  H01L21/225

CPC分类号： H01L29/66803 ,  H01L21/225 ,  H01L21/26526 ,  H01L29/165 ,  H01L29/66818

摘要： Doping techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a fin structure, forming a doped amorphous layer over a portion of the fin structure, and performing a knock-on implantation process to drive a dopant from the doped amorphous layer into the portion of the fin structure, thereby forming a doped feature. The doped amorphous layer includes a non-crystalline form of a material. In some implementations, the knock-on implantation process crystallizes at least a portion of the doped amorphous layer, such that the portion of the doped amorphous layer becomes a part of the fin structure. In some implementations, the doped amorphous layer includes amorphous silicon, and the knock-on implantation process crystallizes a portion of the doped amorphous silicon layer.