公开(公告)号：US11814730B2

公开(公告)日：2023-11-14

申请号：US16618563

申请日：2018-06-01

Applicant: WARNER BABCOCK INSTITUTE FOR GREEN CHEMISTRY, LLC

Inventor： John C. Warner ,  Emily Stoler ,  Dwight Tshudy ,  David Wolf

IPC: C23C18/12 ,  C23C18/14 ,  C23C18/06 ,  H01L21/02 ,  H01L29/24 ,  H01L29/66

CPC classification number: C23C18/1216 ,  C23C18/06 ,  C23C18/127 ,  C23C18/1254 ,  C23C18/143 ,  C23C18/145 ,  H01L21/02 ,  H01L21/02554 ,  H01L21/02565 ,  H01L29/24 ,  H01L29/66

Abstract: Described herein is a technology for the creation of “smooth” metal oxide films or coatings using organic cross-linking agents to enable low-temperature sintering. These metal oxide films can be used in conjunction with low-melting temperature substrates, such as plastics, metal, metal oxide, and glass, providing exquisite control over surface roughness.

公开(公告)号：US20190189795A1

公开(公告)日：2019-06-20

申请号：US16327728

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Aaron D. Lilak ,  Rishabh Mehandru ,  Patrick Morrow ,  Patrick H. Keys

IPC: H01L29/78 ,  H01L21/304 ,  H01L21/762 ,  H01L21/768 ,  H01L21/78 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/02 ,  H01L21/302 ,  H01L21/304 ,  H01L21/762 ,  H01L21/768 ,  H01L21/76802 ,  H01L21/78 ,  H01L29/66 ,  H01L29/66795

Abstract: Methods and apparatus to remove epitaxial defects in semiconductors are disclosed. A disclosed example multilayered die structure includes a fin having a first material, where the fin is epitaxially grown from a first substrate layer having a second material, and where a defect portion of the fin is etched or polished. The disclosed example multilayered die structure also includes a second substrate layer having an opening through which the fin extends.

公开(公告)号：US10083839B2

公开(公告)日：2018-09-25

申请号：US15647689

申请日：2017-07-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng

IPC: H01L21/308 ,  H01L29/78 ,  H01L29/66 ,  H01L21/3065

CPC classification number: H01L21/3088 ,  H01L21/0337 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/31138 ,  H01L21/32105 ,  H01L21/823468 ,  H01L21/823821 ,  H01L27/0924 ,  H01L27/1104 ,  H01L27/1211 ,  H01L29/66 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7851 ,  H01L29/786

Abstract: A method of fabricating semiconductor fins, including, patterning a film stack to produce one or more sacrificial mandrels having sidewalls, exposing the sidewall on one side of the one or more sacrificial mandrels to an ion beam to make the exposed sidewall more susceptible to oxidation, oxidizing the opposite sidewalls of the one or more sacrificial mandrels to form a plurality of oxide pillars, removing the one or more sacrificial mandrels, forming spacers on opposite sides of each of the plurality of oxide pillars to produce a spacer pattern, removing the plurality of oxide pillars, and transferring the spacer pattern to the substrate to produce a plurality of fins.

公开(公告)号：US20180233585A1

公开(公告)日：2018-08-16

申请号：US15945578

申请日：2018-04-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Guillaume Bouche ,  Andy Chih-Hung Wei

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/768 ,  H01L29/40 ,  H01L29/08

CPC classification number: H01L29/66795 ,  H01L21/76804 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/41791 ,  H01L29/66 ,  H01L29/785

Abstract: Provided are approaches for forming merged gate and source/drain (S/D) contacts in a semiconductor device. Specifically, one approach provides a dielectric layer over a set of gate structures formed over a substrate; a set of source/drain (S/D) openings patterned in the dielectric layer between the gate structures; a fill material formed over the gate structures, including within the S/D openings; and a set of gate openings patterned over the gate structures, wherein a portion of the dielectric layer directly adjacent the fill material formed within one of the S/D openings is removed. The fill material is then removed, selective to the dielectric layer, and a metal material is deposited over the semiconductor device to form a set of gate contacts within the gate openings, and a set of S/D contacts within the S/D openings, wherein one of the gate contacts and one of the S/D contacts are merged.

公开(公告)号：US20180166570A1

公开(公告)日：2018-06-14

申请号：US15839024

申请日：2017-12-12

Applicant: Applied Materials, Inc.

Inventor： Sheng-Chin KUNG ,  Hua CHUNG

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L29/161 ,  H01L29/10

CPC classification number: H01L29/7848 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/0262 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/66 ,  H01L29/66795 ,  H01L29/785

Abstract: The present disclosure generally relates to devices having conformal semiconductor cladding materials, and methods of forming the same. The cladding material is a silicon germanium epitaxial material. The cladding material is capable of being deposited to a thickness which is less than cladding materials formed by conventional deposition/etch techniques.

公开(公告)号：US20180166541A1

公开(公告)日：2018-06-14

申请号：US15632842

申请日：2017-06-26

Applicant: Hyundai Motor Company ,  Kia Motors Corporation

Inventor： Dae Hwan Chun

IPC: H01L29/16 ,  H01L29/78 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/1608 ,  H01L29/4236 ,  H01L29/66 ,  H01L29/66068 ,  H01L29/7802 ,  H01L29/7827 ,  H01L29/7831

Abstract: A semiconductor device is provided. The semiconductor device includes a n− type layer disposed at a first surface of a n+ type silicon carbide substrate and a trench disposed at the n− type layer. Additionally, a first gate electrode and a second gate electrode are disposed in the trench and separated from each other. A source electrode is insulated from the first gate electrode and the second gate electrode. Further, the semiconductor includes a drain electrode that is disposed at a second surface of the n+ type silicon carbide substrate, a first channel disposed adjacent to a side surface of the trench and a second channel disposed under the lower surface of the trench. The first channel and the second channel are separated from each other.

公开(公告)号：US20180166324A1

公开(公告)日：2018-06-14

申请号：US15833781

申请日：2017-12-06

Applicant: Infineon Technologies AG

Inventor： Carsten Schaeffer ,  Andreas Moser ,  Matthias Kuenle ,  Matteo Dainese ,  Roland Rupp ,  Hans-Joachim Schulze

IPC: H01L21/762 ,  H01L21/3065 ,  H01L29/08 ,  H01L29/10 ,  H01L21/265 ,  H01L21/02 ,  H01L21/306 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L21/76248 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02595 ,  H01L21/02647 ,  H01L21/02667 ,  H01L21/26513 ,  H01L21/30604 ,  H01L21/30625 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/762 ,  H01L21/823481 ,  H01L21/823487 ,  H01L21/84 ,  H01L27/088 ,  H01L27/1207 ,  H01L29/06 ,  H01L29/0649 ,  H01L29/08 ,  H01L29/0804 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/10 ,  H01L29/1095 ,  H01L29/66 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7393 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7812 ,  H01L29/7813

Abstract: A method of fabricating a semiconductor device includes forming a buried insulation region within a substrate by processing the substrate using etching and deposition processes. A semiconductor layer is formed over the buried insulation region at a first side of the substrate. Device regions are formed in the semiconductor layer. The substrate is thinned from a second side of the substrate to expose the buried insulation region. The buried insulation region is selectively removed to expose a bottom surface of the substrate. A conductive region is formed under the bottom surface of the substrate.

公开(公告)号：US09972697B2

公开(公告)日：2018-05-15

申请号：US15267887

申请日：2016-09-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Takashi Ando ,  Eduard A. Cartier ,  Kisik Choi ,  Vijay Narayanan

IPC: H01L21/3205 ,  H01L29/66 ,  H01L21/28 ,  H01L21/324 ,  H01L29/423 ,  H01L21/321 ,  H01L21/02

CPC classification number: H01L29/66545 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02595 ,  H01L21/28017 ,  H01L21/28088 ,  H01L21/32055 ,  H01L21/321 ,  H01L21/324 ,  H01L29/4232 ,  H01L29/66 ,  H01L29/66795 ,  H01L29/6681

Abstract: A method of fabricating a replacement gate stack for a semiconductor device includes the following steps after removal of a dummy gate: growing a high-k dielectric layer over the area vacated by the dummy gate; depositing a thin metal layer over the high-k dielectric layer; depositing a sacrificial layer over the thin metal layer; performing a first rapid thermal anneal; removing the sacrificial layer; and depositing a metal layer of low resistivity metal for gap fill.

公开(公告)号：US09893154B2

公开(公告)日：2018-02-13

申请号：US15609295

申请日：2017-05-31

Applicant: GLOBALFOUNDRIES INC.

Inventor： Timothy J. McArdle ,  Judson R. Holt ,  Junli Wang

IPC: H01L21/00 ,  H01L29/161 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L29/04

CPC classification number: H01L29/161 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/0245 ,  H01L21/02494 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/04 ,  H01L29/045 ,  H01L29/10 ,  H01L29/1054 ,  H01L29/66 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785

Abstract: Semiconductor device fabrication method and structures are provided having a substrate structure which includes a silicon layer at an upper portion. The silicon layer is recessed in a first region of the substrate structure and remains unrecessed in a second region of the substrate structure. A protective layer having a first germanium concentration is formed above the recessed silicon layer in the first region, which extends along a sidewall of the unrecessed silicon layer of the second region. A semiconductor layer having a second germanium concentration is disposed above the protective layer in the first region of the substrate structure, where the first germanium concentration of the protective layer inhibits lateral diffusion of the second germanium concentration from the semiconductor layer in the first region into the unrecessed silicon layer in the second region of the substrate structure.

公开(公告)号：US09793272B2

公开(公告)日：2017-10-17

申请号：US15170299

申请日：2016-06-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  RENESAS ELECTRONICS CORPORATION

Inventor： Dechao Guo ,  Shogo Mochizuki ,  Andreas Scholze ,  Chun-Chen Yeh

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/165 ,  H01L21/225 ,  H01L21/324 ,  H01L29/267

CPC classification number: H01L29/0847 ,  H01L21/2252 ,  H01L21/324 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/0886 ,  H01L29/08 ,  H01L29/0843 ,  H01L29/086 ,  H01L29/0869 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/165 ,  H01L29/267 ,  H01L29/66 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66681 ,  H01L29/66795 ,  H01L29/7816 ,  H01L29/7833 ,  H01L29/7848 ,  H01L29/7851

Abstract: A semiconductor device including a gate structure on a channel region portion of a fin structure, and at least one of an epitaxial source region and an epitaxial drain region on a source region portion and a drain region portion of the fin structure. At least one of the epitaxial source region portion and the epitaxial drain region portion include a first concentration doped portion adjacent to the fin structure, and a second concentration doped portion on the first concentration doped portion. The second concentration portion has a greater dopant concentration than the first concentration doped portion. An extension dopant region extending into the channel portion of the fin structure having an abrupt dopant concentration gradient of n-type or p-type dopants of 7 nm per decade or greater.