公开(公告)号：US20140264876A1

公开(公告)日：2014-09-18

申请号：US14287533

申请日：2014-05-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vivian W. Ryan ,  Xunyuan Zhang ,  Paul R. Besser

IPC: H01L23/532 ,  H01L23/00

CPC classification number: H01L23/53209 ,  H01L21/02697 ,  H01L21/76846 ,  H01L21/76858 ,  H01L21/76873 ,  H01L21/76886 ,  H01L23/53238 ,  H01L23/5384 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a recess defined in a dielectric layer and an interconnect structure defined in the recess. The interconnect structure includes a first barrier layer lining the recess, the first barrier layer including an alloy of tantalum and a first transition metal other than tantalum, wherein a first interface between the first barrier layer and the dielectric layer has a first stress level. A second barrier layer is positioned on the first barrier layer, the second barrier layer including at least one of tantalum and tantalum nitride, wherein a second interface between the second barrier layer and the first barrier layer has a second stress level that is less than the first stress level. The interconnect structure further includes a fill material substantially filling the recess.

Abstract translation: 半导体器件包括限定在介电层中的凹部和限定在凹部中的互连结构。 所述互连结构包括衬在所述凹部中的第一阻挡层，所述第一阻挡层包括钽合金和除了钽之外的第一过渡金属，其中所述第一阻挡层和所述介电层之间的第一界面具有第一应力水平。 第二阻挡层位于第一阻挡层上，第二阻挡层包括钽和氮化钽中的至少一个，其中第二阻挡层和第一阻挡层之间的第二界面具有小于第二阻挡层的第二应力水平 第一压力水平。 互连结构还包括基本上填充凹部的填充材料。

公开(公告)号：US20140217591A1

公开(公告)日：2014-08-07

申请号：US14247375

申请日：2014-04-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vivian W. Ryan ,  Xunyuan Zhang ,  Paul R. Besser

IPC: H01L23/498

CPC classification number: H01L23/49866 ,  H01L21/76846 ,  H01L21/76858 ,  H01L21/76873 ,  H01L21/76886 ,  H01L23/49827 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a dielectric layer positioned above a substrate of the semiconductor device and a recess defined in the dielectric layer. An adhesion barrier layer is positioned on and in direct contact with at least the sidewalls of the recess, a barrier layer interface being defined where the adhesion barrier layer directly contacts the dielectric layer. A stress-reducing barrier layer is positioned adjacent to the adhesion barrier layer, wherein the stress-reducing barrier layer is adapted to reduce a stress level across the barrier layer interface from a first stress level to a second stress level that is less than the first stress level. At least one layer of a conductive fill material is positioned over the stress-reducing barrier layer, the at least one layer of the conductive fill material substantially filling the recess.

Abstract translation: 半导体器件包括位于半导体器件的衬底上方的电介质层和限定在电介质层中的凹部。 粘合阻挡层定位在至少凹部的侧壁上并与其直接接触，限定粘合阻障层直接接触电介质层的阻挡层界面。 应力降低阻挡层定位成与粘附阻挡层相邻，其中应力降低阻挡层适于将穿过阻挡层界面的应力水平从第一应力水平降低到小于第一应力水平的第二应力水平 压力水平。 导电填充材料的至少一层位于应力减小阻挡层上方，导电填充材料的至少一层基本上填充凹部。

公开(公告)号：US08772158B2

公开(公告)日：2014-07-08

申请号：US13770026

申请日：2013-02-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vivian W. Ryan ,  Xunyuan Zhang ,  Paul R. Besser

IPC: H01L21/44 ,  H01L21/4763

CPC classification number: H01L23/53209 ,  H01L21/02697 ,  H01L21/76846 ,  H01L21/76858 ,  H01L21/76873 ,  H01L21/76886 ,  H01L23/53238 ,  H01L23/5384 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure is generally directed to multi-layer barrier layer stacks for interconnect structures that may be used to reduce mechanical stress levels between the interconnect structure and a dielectric material layer in which the interconnect structure is formed. One illustrative method disclosed herein includes forming a recess in a dielectric layer of a substrate and forming an adhesion barrier layer including an alloy of tantalum and at least one transition metal other than tantalum to line the recess, wherein forming the adhesion barrier layer includes creating a first stress level across a first interface between the adhesion barrier layer and the dielectric layer. The method also includes forming a stress-reducing barrier layer including tantalum over the adhesion barrier layer, wherein the stress-reducing barrier layer reduces the first stress level to a second stress level less than the first stress level, and filling the recess with a fill layer.

Abstract translation: 本公开通常涉及用于互连结构的多层势垒层堆叠，其可用于减小互连结构与其中形成互连结构的介电材料层之间的机械应力水平。 本文公开的一种说明性方法包括在基底的电介质层中形成凹陷，并形成包含钽和至少一种不同于钽的过渡金属的合金的粘合阻挡层，以使凹槽成直线，其中形成粘合阻挡层包括形成 在粘合阻挡层和电介质层之间的第一界面上的第一应力水平。 该方法还包括在粘合阻挡层上形成包括钽的应力减小阻挡层，其中减小应力的阻挡层将第一应力水平降低到小于第一应力水平的第二应力水平，并且用填充物填充凹部 层。

公开(公告)号：US20140167264A1

公开(公告)日：2014-06-19

申请号：US13714049

申请日：2012-12-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Paul R. Besser ,  Mark V. Raymond ,  Valli Arunachalam ,  Hoon Kim

IPC: H01L21/283 ,  H01L29/49

CPC classification number: H01L29/4916 ,  H01L21/28518 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate and forming fins over the semiconductor substrate. Each fin is formed with sidewalls. The method further includes conformally depositing a metal film stack on the sidewalls of each fin. In the method, the metal film stack is annealed to form a metal silicide film over the sidewalls of each fin.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个实施例中，制造集成电路的方法包括提供半导体衬底并在半导体衬底上形成翅片。 每个翅片形成有侧壁。 该方法还包括在每个翅片的侧壁上共形沉积金属膜堆叠。 在该方法中，金属膜堆叠被退火以在每个翅片的侧壁上形成金属硅化物膜。