公开(公告)号：US20140167264A1

公开(公告)日：2014-06-19

申请号：US13714049

申请日：2012-12-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Paul R. Besser ,  Mark V. Raymond ,  Valli Arunachalam ,  Hoon Kim

IPC: H01L21/283 ,  H01L29/49

CPC classification number: H01L29/4916 ,  H01L21/28518 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate and forming fins over the semiconductor substrate. Each fin is formed with sidewalls. The method further includes conformally depositing a metal film stack on the sidewalls of each fin. In the method, the metal film stack is annealed to form a metal silicide film over the sidewalls of each fin.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个实施例中，制造集成电路的方法包括提供半导体衬底并在半导体衬底上形成翅片。 每个翅片形成有侧壁。 该方法还包括在每个翅片的侧壁上共形沉积金属膜堆叠。 在该方法中，金属膜堆叠被退火以在每个翅片的侧壁上形成金属硅化物膜。

公开(公告)号：US20140154877A1

公开(公告)日：2014-06-05

申请号：US13689844

申请日：2012-11-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Paul R. Besser ,  Sean X. Lin ,  Valli Arunachalam

IPC: H01L29/66

CPC classification number: H01L29/66666 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: Methods for fabricating integrated circuits having low resistance metal gate structures are provided. One method includes forming a metal gate stack in a FET trench formed in a FET region. The metal gate stack is etched to form a recessed metal gate stack and a recess. The recess is defined by sidewalls in the FET region and is disposed above the recessed metal gate stack. A liner is formed overlying the sidewalls and the recessed metal gate stack and defines an inner cavity in the recess. A copper layer is formed overlying the liner and at least partially fills the inner cavity. The copper layer is etched to expose an upper portion of the liner while leaving a copper portion disposed in a bottom portion of the inner cavity. Copper is electrolessly deposited on the copper portion to fill a remaining portion of the inner cavity.

Abstract translation: 提供了具有低电阻金属栅极结构的集成电路制造方法。 一种方法包括在FET区域中形成的FET沟槽中形成金属栅叠层。 金属栅极堆叠被蚀刻以形成凹陷的金属栅极堆叠和凹陷。 凹槽由FET区域中的侧壁限定，并设置在凹陷金属栅极堆叠的上方。 衬套形成在侧壁和凹入的金属门叠层之上，并且在凹槽中限定内腔。 铜层形成在衬垫上方并且至少部分地填充内腔。 蚀刻铜层以露出衬套的上部，同时留下设置在内腔的底部中的铜部分。 铜无电沉积在铜部分上以填充内腔的剩余部分。

公开(公告)号：US09142633B2

公开(公告)日：2015-09-22

申请号：US13714049

申请日：2012-12-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Paul R. Besser ,  Mark V. Raymond ,  Valli Arunachalam ,  Hoon Kim

IPC: H01L21/283 ,  H01L29/49 ,  H01L21/285 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/4916 ,  H01L21/28518 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate and forming fins over the semiconductor substrate. Each fin is formed with sidewalls. The method further includes conformally depositing a metal film stack on the sidewalls of each fin. In the method, the metal film stack is annealed to form a metal silicide film over the sidewalls of each fin.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个实施例中，制造集成电路的方法包括提供半导体衬底并在半导体衬底上形成翅片。 每个翅片形成有侧壁。 该方法还包括在每个翅片的侧壁上共形沉积金属膜堆叠。 在该方法中，金属膜堆叠被退火以在每个翅片的侧壁上形成金属硅化物膜。

公开(公告)号：US08691689B1

公开(公告)日：2014-04-08

申请号：US13689839

申请日：2012-11-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Paul R. Besser ,  Sean X. Lin ,  Valli Arunachalam

IPC: H01L21/44

CPC classification number: H01L29/66575 ,  H01L21/76846 ,  H01L21/76864 ,  H01L21/76865 ,  H01L21/76874 ,  H01L21/76879 ,  H01L21/76883 ,  H01L29/665

Abstract: Methods for fabricating integrated circuits having low resistance device contacts are provided. One method includes depositing an ILD layer of insulating material overlying a device region that includes a metal silicide region. The ILD layer is etched to form a sidewall that defines a contact opening formed through the ILD layer exposing the metal silicide region. A liner is formed overlying the sidewall and the metal silicide region and defines an inner cavity in the contact opening. A copper layer is formed overlying the liner and at least partially filling the inner cavity. The copper layer is etched to expose an upper portion of the liner while leaving a copper portion disposed in a bottom portion of the inner cavity. Copper is electrolessly deposited on the copper portion to fill a remaining portion of the inner cavity.

Abstract translation: 提供了制造具有低电阻器件触点的集成电路的方法。 一种方法包括沉积覆盖在包括金属硅化物区域的器件区域上的绝缘材料的ILD层。 蚀刻ILD层以形成侧壁，其限定通过暴露金属硅化物区域的ILD层形成的接触开口。 衬垫形成在侧壁和金属硅化物区域上方并且限定了接触开口中的内腔。 铜层形成在衬垫上方并且至少部分地填充内腔。 蚀刻铜层以露出衬套的上部，同时留下设置在内腔的底部中的铜部分。 铜无电沉积在铜部分上以填充内腔的剩余部分。

公开(公告)号：US08778789B2

公开(公告)日：2014-07-15

申请号：US13689844

申请日：2012-11-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Paul R. Besser ,  Sean X. Lin ,  Valli Arunachalam

IPC: H01L21/3205

CPC classification number: H01L29/66666 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: Methods for fabricating integrated circuits having low resistance metal gate structures are provided. One method includes forming a metal gate stack in a FET trench formed in a FET region. The metal gate stack is etched to form a recessed metal gate stack and a recess. The recess is defined by sidewalls in the FET region and is disposed above the recessed metal gate stack. A liner is formed overlying the sidewalls and the recessed metal gate stack and defines an inner cavity in the recess. A copper layer is formed overlying the liner and at least partially fills the inner cavity. The copper layer is etched to expose an upper portion of the liner while leaving a copper portion disposed in a bottom portion of the inner cavity. Copper is electrolessly deposited on the copper portion to fill a remaining portion of the inner cavity.

Abstract translation: 提供了具有低电阻金属栅极结构的集成电路制造方法。 一种方法包括在FET区域中形成的FET沟槽中形成金属栅叠层。 金属栅极堆叠被蚀刻以形成凹陷的金属栅极堆叠和凹陷。 凹槽由FET区域中的侧壁限定，并设置在凹陷金属栅极堆叠的上方。 衬套形成在侧壁和凹入的金属门叠层之上，并且在凹槽中限定内腔。 铜层形成在衬垫上方并且至少部分地填充内腔。 蚀刻铜层以露出衬套的上部，同时留下设置在内腔的底部中的铜部分。 铜无电沉积在铜部分上以填充内腔的剩余部分。