公开(公告)号：US20240363707A1

公开(公告)日：2024-10-31

申请号：US18769182

申请日：2024-07-10

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih-Wen HUANG ,  Chung-Ting KO ,  Hong-Hsien KE ,  Chia-Hui LIN ,  Tai-Chun HUANG

IPC分类号： H01L29/417 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3115 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/41791 ,  H01L21/02063 ,  H01L21/0217 ,  H01L21/02321 ,  H01L21/0234 ,  H01L21/02343 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/3115 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/823431 ,  H01L21/823475 ,  H01L29/0847 ,  H01L29/41766 ,  H01L29/45 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/7848

摘要： A semiconductor device is provided. The semiconductor device includes a source/drain structure, a contact structure, a glue layer, a barrier layer, and a silicide layer. The contact structure is over the source/drain structure. The glue layer surrounds the contact structure. The barrier layer is formed on at least a portion of a sidewall surface of the contact structure. The silicide layer is between the source/drain structure and the contact structure, and the silicide layer is in direct contact with the glue layer. The bottom surface of the glue layer is lower than the top surface of the source/drain structure and the bottom surface of the barrier layer.

公开(公告)号：US20240363429A1

公开(公告)日：2024-10-31

申请号：US18771662

申请日：2024-07-12

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yun Lee ,  Chung-Ting Ko ,  Chen-Ming Lee ,  Mei-Yun Wang ,  Fu-Kai Yang

IPC分类号： H01L21/8234 ,  H01L21/285 ,  H01L21/768 ,  H01L23/485 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/088 ,  H01L29/417 ,  H01L29/66

CPC分类号： H01L21/823475 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/823431 ,  H01L21/823481 ,  H01L23/485 ,  H01L23/53209 ,  H01L27/0886 ,  H01L29/66795 ,  H01L21/76805 ,  H01L21/76855 ,  H01L23/5226 ,  H01L23/5283 ,  H01L29/41791

摘要： A semiconductor device includes a fin disposed on a substrate, a first dielectric layer disposed over the fin, a first contact extending through the first dielectric layer to a first depth and electrically coupled to the fin, and a second contact extending through the first dielectric layer to a second depth different than the first depth. The first contact has a first bottom portion having a first cross-sectional shape profile. The second contact being electrically isolated from the fin and having a second bottom portion having a second cross-sectional shape profile different than the first cross-sectional shape profile. The semiconductor device also includes a first protective layer disposed along the first contact without being disposed on at least a portion of the first bottom portion of the first contact, and a second protective layer disposed along the second contact including along the second bottom portion of the second contact.

公开(公告)号：US12131949B2

公开(公告)日：2024-10-29

申请号：US18362676

申请日：2023-07-31

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yen-Yu Chen ,  Chung-Liang Cheng

IPC分类号： H01L21/768 ,  H01L21/225 ,  H01L21/311 ,  H01L29/40 ,  H01L29/417 ,  H01L29/45

CPC分类号： H01L21/76879 ,  H01L21/2254 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76865 ,  H01L21/76876 ,  H01L21/76882 ,  H01L29/401 ,  H01L29/41791 ,  H01L21/31122 ,  H01L21/76831 ,  H01L29/456

摘要： A method includes etching a dielectric layer to form a trench in the dielectric layer, depositing a metal layer extending into the trench, performing a nitridation process on the metal layer to convert a portion of the metal layer into a metal nitride layer, performing an oxidation process on the metal nitride layer to form a metal oxynitride layer, removing the metal oxynitride layer, and filling a metallic material into the trench using a bottom-up deposition process to form a contact plug.

公开(公告)号：US20240347636A1

公开(公告)日：2024-10-17

申请号：US18754507

申请日：2024-06-26

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsin-Yi LEE ,  Cheng-Lung HUNG ,  Ji-Cheng CHEN ,  Weng CHANG ,  Chi On CHUI

IPC分类号： H01L29/78 ,  H01L29/417 ,  H01L29/66

CPC分类号： H01L29/785 ,  H01L29/41791 ,  H01L29/66795 ,  H01L2029/7858

摘要： A semiconductor device with different gate structure configurations and a method of fabricating the same are disclosed. The semiconductor device includes a fin structure disposed on a substrate, a nanostructured channel region disposed on the fin structure, and a gate-all-around (GAA) structure surrounding the nanostructured channel region. The GAA structure includes a high-K (HK) gate dielectric layer with a metal doped region having dopants of a first metallic material, a p-type work function metal (pWFM) layer disposed on the HK gate dielectric layer, a bimetallic nitride layer interposed between the HK gate dielectric layer and the pWFM layer, an n-type work function metal (nWFM) layer disposed on the pWFM layer, and a gate metal fill layer disposed on the nWFM layer. The pWFM layer includes a second metallic material and the bimetallic nitride layer includes the first and second metallic materials.

公开(公告)号：US12119392B2

公开(公告)日：2024-10-15

申请号：US18446905

申请日：2023-08-09

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shahaji B. More ,  Shih-Chieh Chang

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L21/04 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/417 ,  H01L29/78

CPC分类号： H01L29/66795 ,  H01L21/02603 ,  H01L21/0455 ,  H01L21/823431 ,  H01L29/0669 ,  H01L29/41791 ,  H01L29/7856 ,  H01L2029/7858

摘要： Methods are disclosed for forming a multi-layer structure including highly controlled diffusion interfaces between alternating layers of different semiconductor materials. According to embodiments, during a deposition of semiconductor layers, the process is controlled to remain at low temperatures such that an inter-diffusion rate between the materials of the deposited layers is managed to provide diffusion interfaces with abrupt Si/SiGe interfaces. The highly controlled interfaces and first and second layers provide a multi-layer structure with improved etching selectivity. In an embodiment, a gate all-around (GAA) transistor is formed with horizontal nanowires (NWs) from the multi-layer structure with improved etching selectivity. In embodiments, horizontal NWs of a GAA transistor may be formed with substantially the same size diameters and silicon germanium (SiGe) NWs may be formed with “all-in-one” silicon (Si) caps.

公开(公告)号：US20240339356A1

公开(公告)日：2024-10-10

申请号：US18744961

申请日：2024-06-17

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuo-Chiang TSAI ,  Fu-Hsiang SU ,  Ke-Jing YU ,  Jyh-Huei CHEN

IPC分类号： H01L21/768 ,  H01L29/417 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/7682 ,  H01L21/76802 ,  H01L21/76831 ,  H01L29/41775 ,  H01L29/4991 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/41791 ,  H01L29/785

摘要： A semiconductor device structure is provided. The semiconductor device structure includes a gate electrode layer formed over a substrate, and a first insulating capping feature formed over the gate electrode layer. The semiconductor device structure includes a source/drain contact structure formed adjacent to the gate electrode layer and a second insulating capping feature formed over the source/drain contact structure. The second insulating capping feature and the first insulating capping feature are made of different materials, and an air gap directly below and in direct contact with the second insulating capping feature.

公开(公告)号：US20240332393A1

公开(公告)日：2024-10-03

申请号：US18741963

申请日：2024-06-13

申请人： Taiwan Semiconductor Manufacturing Company, LTD.

发明人： Hsu-Kai CHANG ,  Jhih-Rong HUANG ,  Yen-Tien TUNG ,  Chia-Hung CHU ,  Shuen-Shin LIANG ,  Tzer-Min SHEN ,  Pinyen LIN ,  Sung-Li WANG

IPC分类号： H01L29/45 ,  H01L21/285 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/45 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7851

摘要： A semiconductor device with different configurations of contact structures and a method of fabricating the same are disclosed. The semiconductor device includes first and second gate structures disposed on first and second fin structures, first and second source/drain (S/D) regions disposed on the first and second fin structures, first and second contact structures disposed on the first and second S/D regions, and a dipole layer disposed at an interface between the first nWFM silicide layer and the first S/D region. The first contact structure includes a first nWFM silicide layer disposed on the first S/D region and a first contact plug disposed on the first nWFM silicide layer. The second contact structure includes a pWFM silicide layer disposed on the second S/D region, a second nWFM silicide layer disposed on the pWFM silicide layer, and a second contact plug disposed on the pWFM silicide layer.

公开(公告)号：US20240332381A1

公开(公告)日：2024-10-03

申请号：US18382395

申请日：2023-10-20

申请人： Samsung Electronics Co., Ltd.

发明人： Ji Won KANG ,  Chung Hwan SHIN ,  Seong Heum CHOI ,  Rak Hwan KIM

IPC分类号： H01L29/417 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/45 ,  H01L29/775 ,  H01L29/78

CPC分类号： H01L29/41791 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/775 ,  H01L29/7851

摘要： A semiconductor device may include an active pattern extending in a first direction, a gate structure which is placed on the active pattern to be spaced apart from each other in the first direction, and includes a gate electrode and a gate spacer, the gate electrode extending in a second direction intersecting the first direction, a gate contact on the gate structure, a source/drain pattern on the active pattern, a source/drain contact on the source/drain pattern, and a via plug on the source/drain contact. An upper surface of the gate contact and a second upper surface of the via plug may be placed on the same plane. A lower surface of the gate contact and a lower surface of the via plug may be different in height, on the basis of an upper surface of the active pattern.

公开(公告)号：US12107162B2

公开(公告)日：2024-10-01

申请号：US17132293

申请日：2020-12-23

申请人： Winbond Electronics Corp.

发明人： Hung-Yu Wei ,  Pei-Hsiu Peng ,  Kai Jen

IPC分类号： H01L29/78 ,  H01L21/77 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/417 ,  H01L29/66 ,  H01L21/84 ,  H01L27/088

CPC分类号： H01L29/7831 ,  H01L21/77 ,  H01L21/823431 ,  H01L29/66484 ,  H01L29/66795 ,  H01L29/785 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L29/41791

摘要： A multi-gate semiconductor structure and its manufacturing method are provided. The semiconductor structure includes a substrate having an active area and an isolation structure adjacent to the active area. The semiconductor structure includes a gate structure formed on the substrate and a gate dielectric layer between the gate structure and the substrate. The gate structure includes a first part above the top surface of the substrate and a second part connected to the first part. The second part of the gate structure is formed in the isolation structure, wherein the isolation structure is in direct contact with the bottom surface and sidewalls of the second part of the gate structure. A method of manufacturing the semiconductor structure includes partially etching the isolation structure to form a trench exposing the top portion of sidewalls of the substrate. The gate dielectric layer and the gate structure extend into the trench.

公开(公告)号：US12107134B2

公开(公告)日：2024-10-01

申请号：US18065442

申请日：2022-12-13

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Cheng-Ming Lin ,  Peng-Soon Lim ,  Zi-Wei Fang

IPC分类号： H01L29/417 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/41791 ,  H01L21/823437 ,  H01L21/823842 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L21/823821

摘要： A device includes a semiconductor channel region and a gate structure. The semiconductor channel region is on a substrate. The gate structure is over the semiconductor channel region and comprises a gate dielectric layer, a first gate conductor layer, and a second gate conductor layer. The first gate conductor layer is over the gate dielectric layer. The first gate conductor layer includes oxygen. The second gate conductor layer is over the first gate conductor layer.