公开(公告)号：US11462632B2

公开(公告)日：2022-10-04

申请号：US17130121

申请日：2020-12-22

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Arkadiusz Malinowski ,  Alexander M. Derrickson ,  Ali Razavieh ,  Halting Wang

IPC: H01L29/735 ,  H01L29/08 ,  H01L29/66 ,  H01L29/10

Abstract: A non-uniform base width bipolar junction transistor (BJT) device includes: a semiconductor substrate, the semiconductor substrate having an upper surface; and a BJT device, the BJT device comprising a collector region, a base region, and an emitter region positioned in the semiconductor substrate, the base region being positioned between the collector region and the emitter region; the base region comprising a top surface and a bottom surface, wherein a first width of the top surface of the base region in a base width direction of the BJT device is greater than a second width of the bottom surface of the base region in the base width direction of the BJT device.

公开(公告)号：US11043588B2

公开(公告)日：2021-06-22

申请号：US16413168

申请日：2019-05-15

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Ali Razavieh ,  Ruilong Xie

IPC: H01L29/78 ,  H01L29/16 ,  H01L27/088 ,  H01L29/66

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a vertical field effect transistor with optimized fin size and improved fin stability and methods of manufacture. The structure includes: a fin structure composed of substrate material, the fin structure includes: a trimmed channel region of the substrate material; a top source/drain region above the trimmed channel region and having a larger cross-section than the trimmed channel region; and a bottom source/drain region below the trimmed channel region and having a larger cross-section than the trimmed channel region; and gate material surrounding the trimmed channel region.

公开(公告)号：US20210083049A1

公开(公告)日：2021-03-18

申请号：US16574763

申请日：2019-09-18

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Ali Razavieh ,  Julien Frougier ,  Bradley Morgenfeld

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L21/762 ,  H01L29/786

Abstract: One illustrative transistor device disclosed herein includes a nanowire matrix comprising a plurality of nanowire structures that are arranged in at least one substantially horizontally oriented row and at least two substantially vertically oriented columns, the at least two substantially vertically oriented columns being laterally spaced apart from one another in a gate width direction of the transistor device, each of the plurality of nanowire structures comprising an outer perimeter. This illustrative embodiment of the transistor device further includes a gate structure that is positioned around the outer perimeter of all of the nanowire structures in the matrix, and a gate cap positioned above the gate structure.