公开(公告)号：US11049934B2

公开(公告)日：2021-06-29

申请号：US16574763

申请日：2019-09-18

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Ali Razavieh ,  Julien Frougier ,  Bradley Morgenfeld

IPC: H01L27/12 ,  H01L29/06 ,  H01L29/423 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L21/762 ,  H01L29/786 ,  H01L21/321 ,  H01L21/3105

Abstract: One illustrative transistor device disclosed herein includes a nanowire matrix comprising a plurality of nanowire structures that are arranged in at least one substantially horizontally oriented row and at least two substantially vertically oriented columns, the at least two substantially vertically oriented columns being laterally spaced apart from one another in a gate width direction of the transistor device, each of the plurality of nanowire structures comprising an outer perimeter. This illustrative embodiment of the transistor device further includes a gate structure that is positioned around the outer perimeter of all of the nanowire structures in the matrix, and a gate cap positioned above the gate structure.

公开(公告)号：US10971625B2

公开(公告)日：2021-04-06

申请号：US16458178

申请日：2019-06-30

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Michael V Aquilino ,  Daniel Jaeger ,  Man Gu ,  Bradley Morgenfeld ,  Haiting Wang ,  Kavya Sree Duggimpudi ,  Wang Zheng

IPC: H01L29/08 ,  H01L27/112 ,  H01L29/78 ,  H01L21/822 ,  H01L29/66

Abstract: A semiconductor device is provided, which includes an array of active regions, gate stacks and substantially uniform epitaxial structures. The gate stacks of the array include a first gate stack and a second gate stack over an active region. An active pillar between the first gate stack and the second gate stack, and the active pillar separating two substantially uniform epitaxial structures. A contact structure over the active pillar, positioned equidistant from the first gate stack and the second gate stack.

公开(公告)号：US20210083049A1

公开(公告)日：2021-03-18

申请号：US16574763

申请日：2019-09-18

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Ali Razavieh ,  Julien Frougier ,  Bradley Morgenfeld

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L21/762 ,  H01L29/786

Abstract: One illustrative transistor device disclosed herein includes a nanowire matrix comprising a plurality of nanowire structures that are arranged in at least one substantially horizontally oriented row and at least two substantially vertically oriented columns, the at least two substantially vertically oriented columns being laterally spaced apart from one another in a gate width direction of the transistor device, each of the plurality of nanowire structures comprising an outer perimeter. This illustrative embodiment of the transistor device further includes a gate structure that is positioned around the outer perimeter of all of the nanowire structures in the matrix, and a gate cap positioned above the gate structure.