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    Virtual linebuffers for image signal processors
    11.
    发明授权
    Virtual linebuffers for image signal processors 有权

    公开(公告)号：US10791284B2

    公开(公告)日：2020-09-29

    申请号：US16659702

    申请日：2019-10-22

    Applicant: Google LLC

    Inventor： Qiuling Zhu ,  Ofer Shacham ,  Jason Rupert Redgrave ,  Daniel Frederic Finchelstein ,  Albert Meixner

    IPC: G09G5/36 ,  H04N5/262 ,  G06T1/60 ,  G06T1/20

    Abstract: In a general aspect, an apparatus can include image processing logic (IPL) configured to perform an image processing operation on pixel data corresponding with an image having a width of W pixels and a height of H pixels to produce output pixel data in vertical slices of K pixels using K vertically overlapping stencils of S×S pixels, K being greater than 1 and less than H, S being greater than or equal to 2, and W being greater than S. The apparatus can also include a linebuffer operationally coupled with the IPL, the linebuffer configured to buffer the pixel data for the IPL. The linebuffer can include a full-size buffer having a width of W and a height of (S−1). The linebuffer can also include a sliding buffer having a width of SB and a height of K, SB being greater than or equal to S and less than W.

    VIRTUAL LINEBUFFERS FOR IMAGE SIGNAL PROCESSORS
    12.
    发明申请
    VIRTUAL LINEBUFFERS FOR IMAGE SIGNAL PROCESSORS 审中-公开

    公开(公告)号：US20190238758A1

    公开(公告)日：2019-08-01

    申请号：US16376479

    申请日：2019-04-05

    Applicant: Google LLC

    Inventor： Qiuling Zhu ,  Ofer Shacham ,  Jason Rupert Redgrave ,  Daniel Frederic Finchelstein ,  Albert Meixner

    IPC: H04N5/262 ,  G06T1/20 ,  G06T1/60

    Abstract: In a general aspect, an apparatus can include image processing logic (IPL) configured to perform an image processing operation on pixel data corresponding with an image having a width of W pixels and a height of H pixels to produce output pixel data in vertical slices of K pixels using K vertically overlapping stencils of S×S pixels, K being greater than 1 and less than H, S being greater than or equal to 2, and W being greater than S. The apparatus can also include a linebuffer operationally coupled with the IPL, the linebuffer configured to buffer the pixel data for the IPL. The linebuffer can include a full-size buffer having a width of W and a height of (S−1). The linebuffer can also include a sliding buffer having a width of SB and a height of K, SB being greater than or equal to S and less than W.

    Sheet generator for image processor
    15.
    发明授权
    Sheet generator for image processor 有权

    公开(公告)号：US11140293B2

    公开(公告)日：2021-10-05

    申请号：US16786359

    申请日：2020-02-10

    Applicant: Google LLC

    Inventor： Albert Meixner ,  Jason Rupert Redgrave ,  Ofer Shacham ,  Qiuling Zhu ,  Daniel Frederic Finchelstein

    IPC: H04N1/32 ,  G06T1/60 ,  B41F15/08

    Abstract: A sheet generator circuit is described. The sheet generator includes electronic circuitry to receive a line group of image data including multiple rows of data from a frame of image data. The multiple rows are sufficient in number to encompass multiple neighboring overlapping stencils. The electronic circuitry is to parse the line group into a smaller sized sheet. The electronic circuitry is to load the sheet into a data computation unit having a two dimensional shift array structure coupled to an array of processors.

    CONVOLUTIONAL NEURAL NETWORK ON PROGRAMMABLE TWO DIMENSIONAL IMAGE PROCESSOR
    16.
    发明申请
    CONVOLUTIONAL NEURAL NETWORK ON PROGRAMMABLE TWO DIMENSIONAL IMAGE PROCESSOR 有权

    公开(公告)号：US20210004633A1

    公开(公告)日：2021-01-07

    申请号：US17028097

    申请日：2020-09-22

    Applicant: Google LLC

    Inventor： Ofer Shacham ,  David Patterson ,  William R. Mark ,  Albert Meixner ,  Daniel Frederic Finchelstein ,  Jason Rupert Redgrave

    IPC: G06K9/56 ,  G06T1/60 ,  G06N3/04 ,  G06N3/063 ,  G06F9/30 ,  G06F9/38 ,  G06K9/46 ,  G06T5/20

    Abstract: A method is described that includes executing a convolutional neural network layer on an image processor having an array of execution lanes and a two-dimensional shift register. The two-dimensional shift register provides local respective register space for the execution lanes. The executing of the convolutional neural network includes loading a plane of image data of a three-dimensional block of image data into the two-dimensional shift register. The executing of the convolutional neural network also includes performing a two-dimensional convolution of the plane of image data with an array of coefficient values by sequentially: concurrently multiplying within the execution lanes respective pixel and coefficient values to produce an array of partial products; concurrently summing within the execution lanes the partial products with respective accumulations of partial products being kept within the two dimensional register for different stencils within the image data; and, effecting alignment of values for the two-dimensional convolution within the execution lanes by shifting content within the two-dimensional shift register array.

    Compiler techniques for mapping program code to a high performance, power efficient, programmable image processing hardware platform
    20.
    发明授权
    Compiler techniques for mapping program code to a high performance, power efficient, programmable image processing hardware platform 有权

    公开(公告)号：US10387988B2

    公开(公告)日：2019-08-20

    申请号：US15389113

    申请日：2016-12-22

    Applicant: Google LLC

    Inventor： Albert Meixner ,  Hyunchul Park ,  William R. Mark ,  Daniel Frederic Finchelstein ,  Ofer Shacham

    IPC: G06T1/20 ,  G06F9/50 ,  G06F8/41

    Abstract: A method is described. The method includes compiling program code targeted for an image processor having programmable stencil processors composed of respective two-dimensional execution lane and shift register circuit structures. The program code is to implement a directed acyclic graph and is composed of multiple kernels that are to execute on respective ones of the stencil processors, wherein the compiling includes any of: recognizing there are a different number of kernels in the program code than stencil processors in the image processor; recognizing that at least one of the kernels is more computationally intensive than another one of the kernels; and, recognizing that the program code has resource requirements that exceed the image processor's memory capacity. The compiling further includes in response to any of the recognizing above performing any of: horizontal fusion of kernels; vertical fusion of kernels; fission of one of the kernels into multiple kernels; spatial partitioning of a kernel into multiple spatially partitioned kernels; splitting the directed acyclic graph into smaller graphs.

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