公开(公告)号：US20120018210A1

公开(公告)日：2012-01-26

申请号：US12868686

申请日：2010-08-25

Applicant: GUANG-FENG OU ,  YONG-ZHAO HUANG

Inventor： GUANG-FENG OU ,  YONG-ZHAO HUANG

IPC: H05K1/18

CPC classification number: H05K1/0219 ,  H05K1/0245 ,  H05K2201/09336 ,  H05K2201/09618

Abstract: A printed circuit board includes a reference layer configured to connect to a power or a ground and a dielectric layer stacked on the reference layer. The dielectric layer includes a component surface opposing the reference layer. The component surface forms a differential pairs, a protection runner, and a power runner. The differential pairs include a substantially linear part. The protection runner is intervened between the linear part and the power runner, and is substantially parallel to the differential pairs. The length of the protection runner is approximately equal to that of the linear part. Each of the two ends of the protection runner forms a via that electrically connects the protection runner to the reference layer.

Abstract translation: 印刷电路板包括被配置为连接到电源或接地的参考层和堆叠在参考层上的电介质层。 电介质层包括与参考层相对的部件表面。 部件表面形成差速对，保护转轮和动力转轮。 差分对包括基本线性的部分。 保护跑步者介于线性部分和动力转轮之间，并且基本上平行于差速对。 保护流道的长度大致等于直线部分的长度。 保护流道的两端中的每一端形成将保护流道电连接到参考层的通孔。

公开(公告)号：US20110210803A1

公开(公告)日：2011-09-01

申请号：US12817193

申请日：2010-06-17

Applicant: GUANG-FENG OU

Inventor： GUANG-FENG OU

IPC: H01P3/02

CPC classification number: H05K1/0248 ,  H05K1/0243 ,  H05K1/0245 ,  H05K2201/09263 ,  H05K2201/09272

Abstract: A differential circuit includes a chip with two terminals in two directions, a first differential signal trace, and a second differential signal trace. The first differential signal trace includes a first parallel section and a first unparallel section connecting the first parallel section to a terminal of the chip. The second differential signal trace includes a second parallel section parallel to the first parallel section, a second unparallel section connecting to the second parallel section, and an equalizing section connecting second unparallel section to the another terminal of the chip. The second parallel section is equal to the first parallel section. The total length of the second unparallel section and the equalizing section is equal to the length of the first unparallel section.

Abstract translation: 差分电路包括在两个方向上具有两个端子的芯片，第一差分信号迹线和第二差分信号迹线。 第一差分信号迹线包括将第一并联部分连接到芯片的端子的第一并联部分和第一不平行部分。 第二差分信号迹线包括平行于第一并联部分的第二并联部分，连接到第二平行部分的第二不平行部分和将第二不平行部分连接到芯片的另一端子的均衡部分。 第二平行段等于第一平行段。 第二不平行部分和均衡部分的总长度等于第一不平行部分的长度。

公开(公告)号：US20120242362A1

公开(公告)日：2012-09-27

申请号：US13093869

申请日：2011-04-26

Applicant: ZHI-YONG ZHAO ,  TAI-CHEN WANG ,  GUANG-FENG OU

Inventor： ZHI-YONG ZHAO ,  TAI-CHEN WANG ,  GUANG-FENG OU

IPC: G01R1/067

CPC classification number: G01R31/2808

Abstract: A test apparatus includes a circuit board and an expansion slot. A number of golden fingers are arranged on a first side of the circuit board. A second side of the circuit board is connected to a bottom of the expansion slot. The golden fingers are electrically connected to the expansion slot. A number of first test pads and second test pads are arranged on the circuit board between the first side and the second side. The first and second test pads have different shapes, sizes, and/or colors. The first and second test pads are electrically connected to pins in the expansion slot.

Abstract translation: 测试装置包括电路板和扩展槽。 多个金手指布置在电路板的第一侧上。 电路板的第二面连接到扩展槽的底部。 金手指电连接到扩展槽。 在第一侧和第二侧之间的电路板上布置有多个第一测试焊盘和第二测试焊盘。 第一和第二测试垫具有不同的形状，尺寸和/或颜色。 第一和第二测试焊盘电连接到扩展槽中的引脚。