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    MULTI-FUNCTIONAL EXECUTION LANE FOR IMAGE PROCESSOR
    11.
    发明申请
    MULTI-FUNCTIONAL EXECUTION LANE FOR IMAGE PROCESSOR 审中-公开

    公开(公告)号：US20170242695A1

    公开(公告)日：2017-08-24

    申请号：US15591955

    申请日：2017-05-10

    Applicant: Google Inc.

    Inventor： Artem Vasilyev ,  Jason Rupert Redgrave ,  Albert Meixner ,  Ofer Shacham

    IPC: G06F9/30 ,  G06F15/80

    CPC classification number: G06F9/3001 ,  G06F7/57 ,  G06F9/30014 ,  G06F15/80

    Abstract: An apparatus is described that includes an execution unit having a multiply add computation unit, a first ALU logic unit and a second ALU logic unit. The ALU unit is to perform first, second, third and fourth instructions. The first instruction is a multiply add instruction. The second instruction is to perform parallel ALU operations with the first and second ALU logic units operating simultaneously to produce different respective output resultants of the second instruction. The third instruction is to perform sequential ALU operations with one of the ALU logic units operating from an output of the other of the ALU logic units to determine an output resultant of the third instruction. The fourth instruction is to perform an iterative divide operation in which the first ALU logic unit and the second ALU logic unit operate during to determine first and second division resultant digit values.

    VIRTUAL LINEBUFFERS FOR IMAGE SIGNAL PROCESSORS
    13.
    发明申请
    VIRTUAL LINEBUFFERS FOR IMAGE SIGNAL PROCESSORS 有权
    图像信号处理器的虚拟线路缓存器

    公开(公告)号：US20160219225A1

    公开(公告)日：2016-07-28

    申请号：US14603354

    申请日：2015-01-22

    Applicant: GOOGLE INC.

    Inventor： Qiuling Zhu ,  Ofer Shacham ,  Jason Rupert Redgrave ,  Daniel Frederic Finchelstein ,  Albert Meixner

    IPC: H04N5/262

    CPC classification number: H04N5/262 ,  G06T1/20 ,  G06T1/60

    Abstract: In a general aspect, an apparatus can include image processing logic (IPL) configured to perform an image processing operation on pixel data corresponding with an image having a width of W pixels and a height of H pixels to produce output pixel data in vertical slices of K pixels using K vertically overlapping stencils of S×S pixels, K being greater than 1 and less than H, S being greater than or equal to 2, and W being greater than S. The apparatus can also include a linebuffer operationally coupled with the IPL, the linebuffer configured to buffer the pixel data for the IPL. The linebuffer can include a full-size buffer having a width of W and a height of (S−1). The linebuffer can also include a sliding buffer having a width of SB and a height of K, SB being greater than or equal to S and less than W.

    Abstract translation: 在一般方面，一种装置可以包括图像处理逻辑（IPL），被配置为对与具有W像素的宽度和H像素的高度的图像相对应的像素数据执行图像处理操作，以在垂直切片中产生输出像素数据 K个像素，使用S×S像素的K个垂直重叠的模板，K大于1且小于H，S大于或等于2，并且W大于S.该装置还可以包括线缓冲器，其操作上与 IPL，线缓冲器被配置为缓冲IPL的像素数据。 线缓冲器可以包括宽度为W且高度为（S-1）的全尺寸缓冲器。 线缓冲器还可以包括具有SB的宽度和K的高度的滑动缓冲器，SB大于或等于S且小于W.

    Multi-functional execution lane for image processor
    14.
    发明授权
    Multi-functional execution lane for image processor 有权

    公开(公告)号：US09830150B2

    公开(公告)日：2017-11-28

    申请号：US14960334

    申请日：2015-12-04

    Applicant: Google Inc.

    Inventor： Artem Vasilyev ,  Jason Rupert Redgrave ,  Albert Meixner ,  Ofer Shacham

    IPC: G06F9/30 ,  G06F7/57 ,  G06F15/80

    CPC classification number: G06F9/3001 ,  G06F7/57 ,  G06F9/30014 ,  G06F15/80

    Abstract: An apparatus is described that includes an execution unit having a multiply add computation unit, a first ALU logic unit and a second ALU logic unit. The ALU unit is to perform first, second, third and fourth instructions. The first instruction is a multiply add instruction. The second instruction is to perform parallel ALU operations with the first and second ALU logic units operating simultaneously to produce different respective output resultants of the second instruction. The third instruction is to perform sequential ALU operations with one of the ALU logic units operating from an output of the other of the ALU logic units to determine an output resultant of the third instruction. The fourth instruction is to perform an iterative divide operation in which the first ALU logic unit and the second ALU logic unit operate during to determine first and second division resultant digit values.

    COMPILER MANAGED MEMORY FOR IMAGE PROCESSOR
    15.
    发明申请
    COMPILER MANAGED MEMORY FOR IMAGE PROCESSOR 审中-公开

    公开(公告)号：US20170287105A1

    公开(公告)日：2017-10-05

    申请号：US15625972

    申请日：2017-06-16

    Applicant: Google Inc.

    Inventor： Albert Meixner ,  Hyunchul Park ,  Qiuling Zhu ,  Jason Rupert Redgrave

    IPC: G06T1/60 ,  G06T1/20

    CPC classification number: G06T1/60 ,  G06F9/3887 ,  G06T1/20

    Abstract: A method is described. The method includes repeatedly loading a next sheet of image data from a first location of a memory into a two dimensional shift register array. The memory is locally coupled to the two-dimensional shift register array and an execution lane array having a smaller dimension than the two-dimensional shift register array along at least one array axis. The loaded next sheet of image data keeps within an image area of the two-dimensional shift register array. The method also includes repeatedly determining output values for the next sheet of image data through execution of program code instructions along respective lanes of the execution lane array, wherein, a stencil size used in determining the output values encompasses only pixels that reside within the two-dimensional shift register array.

    SHIFT REGISTER WITH REDUCED WIRING COMPLEXITY
    18.
    发明申请
    SHIFT REGISTER WITH REDUCED WIRING COMPLEXITY 审中-公开

    公开(公告)号：US20170251184A1

    公开(公告)日：2017-08-31

    申请号：US15595403

    申请日：2017-05-15

    Applicant: Google Inc.

    Inventor： Jason Rupert Redgrave

    IPC: H04N9/04 ,  G06F15/173 ,  H03K19/177 ,  H01P5/12 ,  G06F15/80 ,  G11C7/10

    Abstract: A shift register is described. The shift register includes a plurality of cells and register space. The shift register includes circuitry having inputs to receive shifted data and outputs to transmit shifted data, wherein: i) circuitry of cells physically located between first and second logically ordered cells are configured to not perform any logical shift; ii) circuitry of cells coupled to receive shifted data transmitted by an immediately preceding logically ordered cell comprises circuitry for writing into local register space data received at an input assigned an amount of shift specified in a shift command being executed by the shift register, and, iii) circuitry of cells coupled to transmit shifted data to an immediately following logically ordered cell comprises circuitry to transmit data from an output assigned an incremented shift amount from a shift amount of an input that the data was received on.

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