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公开(公告)号：US09756268B2
公开(公告)日：2017-09-05
申请号：US14694712
申请日：2015-04-23
Applicant: Google Inc.
Inventor： Neeti Desai , Albert Meixner , Qiuling Zhu , Jason Rupert Redgrave , Ofer Shacham , Daniel Frederic Finchelstein
CPC classification number: H04N5/3692 , G06T1/60 , H04N5/91
Abstract: An apparatus is described that include a line buffer unit composed of a plurality of a line buffer interface units. Each line buffer interface unit is to handle one or more requests by a respective producer to store a respective line group in a memory and handle one or more requests by a respective consumer to fetch and provide the respective line group from memory. The line buffer unit has programmable storage space whose information establishes line group size so that different line group sizes for different image sizes are storable in memory.
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公开(公告)号：US09749548B2
公开(公告)日：2017-08-29
申请号：US14603354
申请日：2015-01-22
Applicant: GOOGLE INC.
Inventor： Qiuling Zhu , Ofer Shacham , Jason Rupert Redgrave , Daniel Frederic Finchelstein , Albert Meixner
Abstract: In a general aspect, an apparatus can include image processing logic (IPL) configured to perform an image processing operation on pixel data corresponding with an image having a width of W pixels and a height of H pixels to produce output pixel data in vertical slices of K pixels using K vertically overlapping stencils of S×S pixels, K being greater than 1 and less than H, S being greater than or equal to 2, and W being greater than S. The apparatus can also include a linebuffer operationally coupled with the IPL, the linebuffer configured to buffer the pixel data for the IPL. The linebuffer can include a full-size buffer having a width of W and a height of (S−1). The linebuffer can also include a sliding buffer having a width of SB and a height of K, SB being greater than or equal to S and less than W.
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公开(公告)号：US20160313999A1
公开(公告)日：2016-10-27
申请号：US14694815
申请日：2015-04-23
Applicant: Google Inc.
Inventor： Albert Meixner , Jason Rupert Redgrave , Ofer Shacham , Daniel Frederic Finchelstein , Qiuling Zhu
IPC: G06F9/38
CPC classification number: G06F9/3802 , G06F9/3004 , G06F9/30043 , G06F9/30134 , G06F9/38 , G06F9/3836 , G06F9/3851 , G06F9/3871 , G06F9/3885 , G06F9/3887 , G06F15/8023 , G06T1/20 , H04N3/14 , H04N3/1575
Abstract: An apparatus is described. The apparatus includes a program controller to fetch and issue instructions. The apparatus includes an execution lane having at least one execution unit to execute the instructions. The execution lane is part of an execution lane array that is coupled to a two dimensional shift register array structure, wherein, execution lanes of the execution lane array are located at respective array locations and are coupled to dedicated registers at same respective array locations in the two-dimensional shift register array.
Abstract translation: 描述了一种装置。 该装置包括用于获取和发出指令的程序控制器。 该装置包括具有执行指令的至少一个执行单元的执行通道。 执行通道是耦合到二维移位寄存器阵列结构的执行通道阵列的一部分，其中，执行通道阵列的执行通道位于相应的阵列位置处，并且被耦合到专用寄存器中的相应相应阵列位置 二维移位寄存器阵列。
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公开(公告)号：US20160219225A1
公开(公告)日：2016-07-28
申请号：US14603354
申请日：2015-01-22
Applicant: GOOGLE INC.
Inventor： Qiuling Zhu , Ofer Shacham , Jason Rupert Redgrave , Daniel Frederic Finchelstein , Albert Meixner
IPC: H04N5/262
Abstract: In a general aspect, an apparatus can include image processing logic (IPL) configured to perform an image processing operation on pixel data corresponding with an image having a width of W pixels and a height of H pixels to produce output pixel data in vertical slices of K pixels using K vertically overlapping stencils of S×S pixels, K being greater than 1 and less than H, S being greater than or equal to 2, and W being greater than S. The apparatus can also include a linebuffer operationally coupled with the IPL, the linebuffer configured to buffer the pixel data for the IPL. The linebuffer can include a full-size buffer having a width of W and a height of (S−1). The linebuffer can also include a sliding buffer having a width of SB and a height of K, SB being greater than or equal to S and less than W.
Abstract translation: 在一般方面，一种装置可以包括图像处理逻辑（IPL），被配置为对与具有W像素的宽度和H像素的高度的图像相对应的像素数据执行图像处理操作，以在垂直切片中产生输出像素数据 K个像素，使用S×S像素的K个垂直重叠的模板，K大于1且小于H，S大于或等于2，并且W大于S.该装置还可以包括线缓冲器，其操作上与 IPL，线缓冲器被配置为缓冲IPL的像素数据。 线缓冲器可以包括宽度为W且高度为（S-1）的全尺寸缓冲器。 线缓冲器还可以包括具有SB的宽度和K的高度的滑动缓冲器，SB大于或等于S且小于W.
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公开(公告)号：US20170256021A1
公开(公告)日：2017-09-07
申请号：US15599348
申请日：2017-05-18
Applicant: Google Inc.
Inventor： Qiuling Zhu , Ofer Shacham , Albert Meixner , Jason Rupert Redgrave , Daniel Frederic Finchelstein , David Patterson , Neeti Desai , Donald Stark , Edward Chang , William Mark
Abstract: An apparatus is described. The apparatus includes an image processing unit. The image processing unit includes a plurality of stencil processor circuits each comprising an array of execution unit lanes coupled to a two-dimensional shift register array structure to simultaneously process multiple overlapping stencils through execution of program code. The image processing unit includes a plurality of sheet generators respectively coupled between the plurality of stencil processors and the network. The sheet generators are to parse input line groups of image data into input sheets of image data for processing by the stencil processors, and, to form output line groups of image data from output sheets of image data received from the stencil processors. The image processing unit includes a plurality of line buffer units coupled to the network to pass line groups in a direction from producing stencil processors to consuming stencil processors to implement an overall program flow.
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Patent Agency Ranking
公开(公告)号：US20170249153A1
公开(公告)日：2017-08-31
申请号：US15595632
申请日：2017-05-15
Applicant: Google Inc.
Inventor： Albert Meixner , Jason Rupert Redgrave , Ofer Shacham , Daniel Frederic Finchelstein , Qiuling Zhu
CPC classification number: G06F9/3802 , G06F9/3004 , G06F9/30043 , G06F9/30134 , G06F9/38 , G06F9/3836 , G06F9/3851 , G06F9/3871 , G06F9/3885 , G06F9/3887 , G06F15/8023 , G06T1/20 , H04N3/14 , H04N3/1575
Abstract: An apparatus is described. The apparatus includes a program controller to fetch and issue instructions. The apparatus includes an execution lane having at least one execution unit to execute the instructions. The execution lane is part of an execution lane array that is coupled to a two dimensional shift register array structure, wherein, execution lane s of the execution lane array are located at respective array locations and are coupled to dedicated registers at same respective array locations in the two-dimensional shift register array.
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公开(公告)号：US20170206627A1
公开(公告)日：2017-07-20
申请号：US15479159
申请日：2017-04-04
Applicant: Google Inc.
Inventor： Qiuling Zhu , Ofer Shacham , Jason Rupert Redgrave , Daniel Frederic Finchelstein , Albert Meixner
Abstract: In a general aspect, an apparatus can include image processing logic (IPL) configured to perform an image processing operation on pixel data corresponding with an image having a width of W pixels and a height of H pixels to produce output pixel data in vertical slices of K pixels using K vertically overlapping stencils of S×S pixels, K being greater than 1 and less than H, S being greater than or equal to 2, and W being greater than S. The apparatus can also include a linebuffer operationally coupled with the IPL, the linebuffer configured to buffer the pixel data for the IPL. The linebuffer can include a full-size buffer having a width of W and a height of (S-1). The linebuffer can also include a sliding buffer having a width of SB and a height of K, SB being greater than or equal to S and less than W.
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公开(公告)号：US20160316157A1
公开(公告)日：2016-10-27
申请号：US14694712
申请日：2015-04-23
Applicant: Google Inc.
Inventor： Neeti Desai , Albert Meixner , Qiuling Zhu , Jason Rupert Redgrave , Ofer Shacham , Daniel Frederic Finchelstein
CPC classification number: H04N5/3692 , G06T1/60 , H04N5/91
Abstract: An apparatus is described that include a line buffer unit composed of a plurality of a line buffer interface units. Each line buffer interface unit is to handle one or more requests by a respective producer to store a respective line group in a memory and handle one or more requests by a respective consumer to fetch and provide the respective line group from memory. The line buffer unit has programmable storage space whose information establishes line group size so that different line group sizes for different image sizes are storable in memory.
Abstract translation: 描述了包括由多个行缓冲器接口单元组成的行缓冲器单元的装置。 每个行缓冲器接口单元是处理相应制造商的一个或多个请求以将相应的行组存储在存储器中并且处理相应消费者的一个或多个请求以从存储器提取并提供相应的行组。 行缓冲单元具有可编程存储空间，其信息建立线组大小，使得用于不同图像大小的不同线组大小可存储在存储器中。
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公开(公告)号：US20160316094A1
公开(公告)日：2016-10-27
申请号：US14694806
申请日：2015-04-23
Applicant: Google Inc.
Inventor： Albert Meixner , Jason Rupert Redgrave , Ofer Shacham , Qiuling Zhu , Daniel Frederic Finchelstein
CPC classification number: H04N1/32101 , B41F15/0804 , G06T1/60
Abstract: A sheet generator circuit is described. The sheet generator includes electronic circuitry to receive a line group of image data including multiple rows of data from a frame of image data. The multiple rows are sufficient in number to encompass multiple neighboring overlapping stencils. The electronic circuitry is to parse the line group into a smaller sized sheet. The electronic circuitry is to load the sheet into a data computation unit having a two dimensional shift array structure coupled to an array of processors.
Abstract translation: 描述纸张发生器电路。 片材发生器包括电子电路，用于从图像数据的帧接收包括多行数据的线组图像数据。 多行数量足以包含多个相邻的重叠模板。 电子电路将线组解析成较小尺寸的片。 电子电路将片材加载到具有耦合到处理器阵列的二维移位阵列结构的数据计算单元中。
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公开(公告)号：US20170310855A1
公开(公告)日：2017-10-26
申请号：US15590849
申请日：2017-05-09
Applicant: Google Inc.
Inventor： Ofer Shacham , Jason Rupert Redgrave , Albert Meixner , Qiuling Zhu , Daniel Frederic Finchelstein , David Patterson , Donald Stark
CPC classification number: H04N3/1575 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30134 , G06T1/60
Abstract: An apparatus is described. The apparatus includes an execution lane array coupled to a two dimensional shift register array structure. Locations in the execution lane array are coupled to same locations in the two-dimensional shift register array structure such that different execution lanes have different dedicated registers.
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